libvirt supports guest CPU cache by commit df13c0b, So add this feature
to virt-install to configure cpu L3 cache mode.
GUI support will be added later.
Currently, The valid value are 'passthrough', 'emulate' or 'disable'.
say:
--cpu host-passthrough,cachemode=passthrough
--cpu $CPU,cachemode=emulate
--cpu $CPU,cachemode=disable
Signed-off-by: Lin Ma <lma@xxxxxxxx>
---
man/virt-install.pod | 4 ++++
virtinst/cli.py | 12 ++++++++++--
virtinst/cpu.py | 29 +++++++++++++++++++++++++++++
3 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/man/virt-install.pod b/man/virt-install.pod
index 3482e53..49ee9b8 100644
--- a/man/virt-install.pod
+++ b/man/virt-install.pod
@@ -247,6 +247,10 @@ Example of specifying two NUMA cells. This will generate XML like:
</numa>
</cpu>
+=item B<--cpu host-passthrough,cachemode=passthrough>
+
+Example of passing through the host cpu's cache information.
+
=back
Use --cpu=? to see a list of all available sub options. Complete details at L<http://libvirt.org/formatdomain.html#elementsCPU>
diff --git a/virtinst/cli.py b/virtinst/cli.py
index ece9b86..786395f 100644
--- a/virtinst/cli.py
+++ b/virtinst/cli.py
@@ -617,8 +617,9 @@ def vcpu_cli_options(grp, backcompat=True, editexample=False):
if editexample:
extramsg = "--cpu host-model,clearxml=yes"
grp.add_argument("--cpu",
- help=_("CPU model and features. Ex:\n"
- "--cpu coreduo,+x2apic\n") + extramsg)
+ help=_("CPU model, L3 cache mode and features. Ex:\n"
+ "--cpu coreduo,+x2apic\n"
+ "--cpu host-passthrough,cachemode=passthrough\n") + extramsg)
if backcompat:
grp.add_argument("--check-cpu", action="store_true",
@@ -1467,6 +1468,10 @@ class ParserCPU(VirtCLIParser):
else:
inst.add_feature(feature_name, policy)
+ def set_l3_cache_cb(self, inst, val, virtarg):
+ cpu = inst
+ cpu.set_l3_cache_mode(cpu, val)
+
def _parse(self, inst):
# Convert +feature, -feature into expected format
for key, value in self.optdict.items():
@@ -1508,6 +1513,9 @@ ParserCPU.add_arg("cpus", "cell[0-9]*.cpus", can_comma=True,
ParserCPU.add_arg("memory", "cell[0-9]*.memory",
find_inst_cb=ParserCPU.cell_find_inst_cb)
+# Options for CPU.cache
+ParserCPU.add_arg(None, "cachemode", cb=ParserCPU.set_l3_cache_cb)
+
###################
# --vcpus parsing #
diff --git a/virtinst/cpu.py b/virtinst/cpu.py
index 468853f..ec46452 100644
--- a/virtinst/cpu.py
+++ b/virtinst/cpu.py
@@ -32,6 +32,20 @@ class _CPUCell(XMLBuilder):
memory = XMLProperty("./@memory", is_int=True)
+class CPUCache(XMLBuilder):
+ """
+ Class for generating <cpu> child <cache> XML
+ """
+
+ MODES = ["passthrough", "emulate", "disable"]
+
+ _XML_ROOT_NAME = "cache"
+ _XML_PROP_ORDER = ["level", "mode"]
+
+ level = XMLProperty("./@level")
+ mode = XMLProperty("./@mode")
+
+
class CPUFeature(XMLBuilder):
"""
Class for generating <cpu> child <feature> XML
@@ -107,6 +121,21 @@ class CPU(XMLBuilder):
self.add_child(obj)
return obj
+ cache = XMLChildProperty(CPUCache)
+ def set_l3_cache_mode(self, cpu, cache_mode):
+ cache = CPUCache(self.conn)
+ if cache_mode not in ["emulate", "passthrough", "disable"]:
+ raise RuntimeError("valid cache mode: 'passthrough' or "
+ "'emulate' or 'disable'")
+ if cache_mode == "emulate":
+ cache.level = "3"
+ elif (cache_mode == "passthrough" and
+ cpu.mode != self.SPECIAL_MODE_HOST_PASSTHROUGH):
+ raise RuntimeError("cache mode 'passthrough' requires "
+ "CPU model 'host-passthrough'")
+ cache.mode = cache_mode
+ self.add_child(cache)
+
def copy_host_cpu(self):
"""
Enact the equivalent of qemu -cpu host, pulling all info
--
2.9.2
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