Excellent job, thanks a lot!
Could you apply the following patch? That's because the build
on aarch64 machine fails.
$ make lscpu
CC sys-utils/lscpu-lscpu-virt.o
sys-utils/lscpu-virt.c: In function 'lscpu_read_virtualization':
sys-utils/lscpu-virt.c:571:16: error: void value not ignored as it ought to be
virt->vendor = read_hypervisor_cpuid();
^
make: *** [Makefile:11444: sys-utils/lscpu-lscpu-virt.o] Error 1
$
---
sys-utils/lscpu-virt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/sys-utils/lscpu-virt.c b/sys-utils/lscpu-virt.c
index 5dabe031c..527f7caa4 100644
--- a/sys-utils/lscpu-virt.c
+++ b/sys-utils/lscpu-virt.c
@@ -377,8 +377,9 @@ none:
}
#else /* ! (__x86_64__ || __i386__) */
-static void read_hypervisor_cpuid(void)
+static int read_hypervisor_cpuid(void)
{
+ return VIRT_VENDOR_NONE;
}
#endif
--
2.27.0
Thanks,
Masa
On Fri, Nov 13, 2020 at 10:53:52AM +0100, Karel Zak wrote:
>
> Hi guys,
>
> I have merged new lscpu(1) to our master branch. Changes:
>
> * code is more readable and better structured (I hope)
>
> * data about CPU and CPU-type are maintained in separate structs
>
> * supports multiple CPU-types (model and topology) on one system
> (the old version reads topology only from CPU0 only)
>
> Example from system with A53 and A72 with different number of cores:
>
> Vendor ID: ARM
> Model name: Cortex-A53
> Model: 4
> Thread(s) per core: 1
> Core(s) per socket: 4
> Socket(s): 1
> Stepping: r0p4
> CPU max MHz: 1416.0000
> CPU min MHz: 408.0000
> BogoMIPS: 48.00
> Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
> Model name: Cortex-A72
> Model: 2
> Thread(s) per core: 1
> Core(s) per socket: 2
> Socket(s): 1
> Stepping: r0p2
> CPU max MHz: 1800.0000
> CPU min MHz: 408.0000
> BogoMIPS: 48.00
> Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
>
>
> * the default output on the terminal is organized in sections to make
> it more readable for humans, non-terminal output (>file, |grep, etc) is
> still "flat".
>
> * the output for --extended and --parse provides more columns now
>
> * it uses cache IDs as exported by new kernels; it's possible that
> --extended and --parse cache identifiers will not start from zero.
> It's an expected change.
>
> * all recent ARM related changes has been merged into the new code too
>
> I have /sys and /proc dumps from many systems, but it's still possible
> that the new lscpu will print non-senses in some cases. Please, test
> it on your machines, exotic or unusual systems, etc. You know ... ;-)
> Thanks!
>
> Karel
>
> --
> Karel Zak <kzak@xxxxxxxxxx>
> http://karelzak.blogspot.com
>
