On Thu, Mar 13, 2025 at 08:34:41AM +0100, Ahmad Fatoum wrote: > This was detected by clang-analyzer and I don't understand how that > function could have ever worked, because it's running into the zero > division in the "successful" code path. The driver is only tested on rk3568, so this code path likely never executed. sascha > > Peeking at rk3568_set_intf_mux, the CRTC clock is passed by the caller > in barebox, so let's do the same for rk3588_calc_cru_cfg. > > Fixes: c8c0833beb77 ("video: Rockchip: Add VOP2 driver") > Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx> > --- > drivers/video/rockchip/rockchip_drm_vop2.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/video/rockchip/rockchip_drm_vop2.c b/drivers/video/rockchip/rockchip_drm_vop2.c > index 3a1c951ec7e4..f15ef1b57bf5 100644 > --- a/drivers/video/rockchip/rockchip_drm_vop2.c > +++ b/drivers/video/rockchip/rockchip_drm_vop2.c > @@ -743,10 +743,10 @@ static unsigned long rk3588_calc_dclk(unsigned long child_clk, unsigned long max > */ > static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id, > int *dclk_core_div, int *dclk_out_div, > - int *if_pixclk_div, int *if_dclk_div) > + int *if_pixclk_div, int *if_dclk_div, > + u32 crtc_clock) > { > struct vop2 *vop2 = vp->vop2; > - u32 crtc_clock = 0; > unsigned long v_pixclk = crtc_clock * 1000LL; /* video timing pixclk */ > unsigned long dclk_core_rate = v_pixclk >> 2; > unsigned long dclk_rate = v_pixclk; > @@ -856,7 +856,7 @@ static unsigned long rk3588_set_intf_mux(struct vop2_video_port *vp, int id, u32 > u32 die, dip, div, vp_clk_div, val; > > clock = rk3588_calc_cru_cfg(vp, id, &dclk_core_div, &dclk_out_div, > - &if_pixclk_div, &if_dclk_div); > + &if_pixclk_div, &if_dclk_div, clock); > if (!clock) > return 0; > > -- > 2.39.5 > > > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |