clang-analyzer reports that a zero division may be possible while computing post_divr_freq. Bail out early instead by returning -ERANGE. Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx> --- drivers/clk/analogbits/wrpll-cln28hpc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c index 1aafaf2e6502..a9231fbf8188 100644 --- a/drivers/clk/analogbits/wrpll-cln28hpc.c +++ b/drivers/clk/analogbits/wrpll-cln28hpc.c @@ -301,6 +301,9 @@ int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate, c->divr = best_r - 1; c->divf = best_f - 1; + if (!best_r) + return -ERANGE; + post_divr_freq = div_u64(parent_rate, best_r); /* Pick the best PLL jitter filter */ -- 2.39.5
