CONFIG_HAS_CACHE only serves a purpose on RISC-V to allow barebox to run
on softcores without fence.i instruction. Rename the symbol to reflect
that in preparation for removing HAS_CACHE altogether.
Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
---
arch/riscv/Kconfig.socs | 9 ++++++---
arch/riscv/include/asm/cache.h | 2 +-
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index ccda688faf6d..4a3b56b5fff4 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -19,7 +19,7 @@ config SOC_VIRT
bool "QEMU Virt Machine"
select RISCV_S_MODE
select BOARD_GENERIC_DT
- select HAS_CACHE
+ select RISCV_ICACHE
select HAS_DEBUG_LL
help
Generates an image tht can be be booted by QEMU. The image is called
@@ -46,7 +46,7 @@ config BOARD_RISCVEMU
config CPU_SIFIVE
bool
- select HAS_CACHE
+ select RISCV_ICACHE
config SOC_SIFIVE
bool "SiFive SoCs"
@@ -116,7 +116,7 @@ config SOC_ALLWINNER_SUN20I
bool "Allwinner Sun20i SoCs"
depends on ARCH_RV64I
select HAS_DEBUG_LL
- select HAS_CACHE
+ select RISCV_ICACHE
if SOC_ALLWINNER_SUN20I
@@ -130,6 +130,9 @@ endif
comment "CPU features"
+config RISCV_ICACHE
+ bool
+
config SIFIVE_L2
bool "SiFive L2 cache controller"
depends on CPU_SIFIVE
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index c787f890017e..8c3cde669c30 100644
--- a/arch/riscv/include/asm/cache.h
+++ b/arch/riscv/include/asm/cache.h
@@ -21,7 +21,7 @@ static inline void thead_local_flush_icache_all(void)
static inline void local_flush_icache_all(void)
{
-#ifdef CONFIG_HAS_CACHE
+#ifdef CONFIG_RISCV_ICACHE
switch(riscv_vendor_id()) {
case THEAD_VENDOR_ID:
thead_local_flush_icache_all();
--
2.39.5
