Since a previous commit, PCA9450_RESET_CTRL is initialized to 0xA1 in
pca9450_probe; explicitly setting this in board.c has no effect anymore.
Signed-off-by: Jonas Rebmann <jre@xxxxxxxxxxxxxx>
---
arch/arm/boards/phytec-phycore-imx93/board.c | 9 ---------
arch/arm/boards/tqma93xx/board.c | 3 ---
2 files changed, 12 deletions(-)
diff --git a/arch/arm/boards/phytec-phycore-imx93/board.c b/arch/arm/boards/phytec-phycore-imx93/board.c
index 149248ca654624826d0e8f6fe0f1f42c2747e248..03ba8cb5026d2a9eaa054fcfc69e18872fcd658e 100644
--- a/arch/arm/boards/phytec-phycore-imx93/board.c
+++ b/arch/arm/boards/phytec-phycore-imx93/board.c
@@ -6,23 +6,14 @@
#include <init.h>
#include <linux/kernel.h>
#include <environment.h>
-#include <mfd/pca9450.h>
#include <deep-probe.h>
#include <mach/imx/bbu.h>
#include <linux/pinctrl/consumer.h>
-static void phycore_imx93_init_pmic(struct regmap *map)
-{
- /* set WDOG_B_CFG to cold reset */
- regmap_write(map, PCA9450_RESET_CTRL, 0xA1);
-}
-
static int phycore_imx93_probe(struct device *dev)
{
struct device_node *np;
- pca9450_register_init_callback(phycore_imx93_init_pmic);
-
/*
* The phy on the EQOS has its MDIO lines connected to the FEC. The phy
* registers can only be successfully read when the EQOS pinctrl setup
diff --git a/arch/arm/boards/tqma93xx/board.c b/arch/arm/boards/tqma93xx/board.c
index b181784079cf12e5a112d13f95c87c2cf5ebeba6..b4de6c2f6c347cb255537a3784a667a9c2607de3 100644
--- a/arch/arm/boards/tqma93xx/board.c
+++ b/arch/arm/boards/tqma93xx/board.c
@@ -27,9 +27,6 @@ static void tqma93xx_init_pmic(struct regmap *map)
/* I2C_LT_EN*/
regmap_write(map, 0xa, 0x3);
-
- /* set WDOG_B_CFG to cold reset */
- regmap_write(map, PCA9450_RESET_CTRL, 0xA1);
}
static int tqma93xx_probe(struct device *dev)
--
2.39.5
