Hi Konstantin, Am Mittwoch, dem 08.01.2025 um 16:14 +0100 schrieb Konstantin Kletschke: > Hello Sascha, > > On Wed, Jan 08, 2025 at 03:32:04PM +0100, Sascha Hauer wrote: > > > Calling udelay(1000) and adding a comment saying it delays 1.8ms looks > > inconsistent. Maybe better count up to 2 in __udelay() above which makes > > I completely agree somehow since the time is not even constant and depends on > the PLL settings just done before. > > I suggest the following: > > Removing the "* 3" fancy thingy in the function's loop, calling the > function with 3000 instead of 1000, changing comment to "needed on some > Beaglebone Black for warm start after reset". > > That would be as simple as possible. It would be interesting to know if any of the configured PLLs go out of lock again during the time your delay loop runs. I.e. check if any of CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_PER or CM_IDLEST_DPLL_MPU contain a value other than 0x1. Premature signaling of a PLL lock during warm reboot (where the PLL isn't in bypass before the configuration) might well explain the issue. Regards, Lucas