This devicetree is in kernel upstream now. We can drop the barebox
version.
Signed-off-by: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx>
---
arch/arm/dts/stm32mp151-mect1s.dts | 319 +----------------------------
1 file changed, 1 insertion(+), 318 deletions(-)
diff --git a/arch/arm/dts/stm32mp151-mect1s.dts b/arch/arm/dts/stm32mp151-mect1s.dts
index b0dc1cfaa8b6..1f5b5bdba6df 100644
--- a/arch/arm/dts/stm32mp151-mect1s.dts
+++ b/arch/arm/dts/stm32mp151-mect1s.dts
@@ -1,322 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) Protonic Holland
- * Author: David Jander <david@xxxxxxxxxxx>
- */
/dts-v1/;
-#include "arm/st/stm32mp151.dtsi"
-#include "arm/st/stm32mp15xc.dtsi"
-#include "arm/st/stm32mp15-pinctrl.dtsi"
-#include "arm/st/stm32mp15xxaa-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
+#include <arm/st/stm32mp151c-mect1s.dts>
#include "stm32mp151.dtsi"
-
-/ {
- model = "Protonic MECT1S";
- compatible = "prt,mect1s", "st,stm32mp151";
-
- chosen {
- stdout-path = "serial0:1500000n8";
- };
-
- aliases {
- serial0 = &uart4;
- ethernet0 = ðernet0;
- };
-
- v3v3: fixed-regulator-v3v3 {
- compatible = "regulator-fixed";
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- v5v: fixed-regulator-v5v {
- compatible = "regulator-fixed";
- regulator-name = "v5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- clock_sja1105: clock-sja1105 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-
- led {
- compatible = "gpio-leds";
-
- led-0 {
- label = "debug:red";
- gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
- };
-
- led-1 {
- label = "debug:green";
- gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- spi_gpio: spi-gpio-0 {
- compatible = "spi-gpio";
- sck-gpios = <&gpioi 1 GPIO_ACTIVE_HIGH>;
- mosi-gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>;
- miso-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&gpioj 3 GPIO_ACTIVE_LOW>;
- num-chipselects = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-};
-
-&clk_hse {
- clock-frequency = <24000000>;
-};
-
-&clk_lse {
- status = "disabled";
-};
-
-&qspi {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a
- &qspi_bk1_pins_a
- &qspi_cs1_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a
- &qspi_bk1_sleep_pins_a
- &qspi_cs1_sleep_pins_a>;
- status = "okay";
-
- flash@0 {
- compatible = "spi-nor";
- reg = <0>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <104000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&qspi_bk1_pins_a {
- pins1 {
- bias-pull-up;
- drive-push-pull;
- slew-rate = <1>;
- };
-};
-
-ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rgmii_pins_x>;
- pinctrl-1 = <ðernet0_rgmii_sleep_pins_x>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii";
- st,eth-clk-sel;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-
- mdio0: mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- };
-};
-
-&mdio0 {
- /* All this DP83TG720R PHYs can't be probed before switch@0 is
- * probed so we need to use compatible with PHYid
- */
- /* TI DP83TG720R */
- t1_phy0: ethernet-phy@8 {
- compatible = "ethernet-phy-id2000.a284";
- reg = <8>;
- interrupts-extended = <&gpioi 5 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpioh 13 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10>;
- reset-deassert-us = <35>;
- };
-
- /* TI DP83TG720R */
- t1_phy1: ethernet-phy@c {
- compatible = "ethernet-phy-id2000.a284";
- reg = <12>;
- interrupts-extended = <&gpioj 0 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpioh 14 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10>;
- reset-deassert-us = <35>;
- };
-
- /* TI DP83TG720R */
- t1_phy2: ethernet-phy@4 {
- compatible = "ethernet-phy-id2000.a284";
- reg = <4>;
- interrupts-extended = <&gpioi 7 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10>;
- reset-deassert-us = <35>;
- };
-
- /* TI DP83TG720R */
- t1_phy3: ethernet-phy@d {
- compatible = "ethernet-phy-id2000.a284";
- reg = <13>;
- interrupts-extended = <&gpioi 15 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpioi 13 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10000>;
- reset-deassert-us = <1000>;
- };
-};
-
-&spi_gpio {
- switch@0 {
- compatible = "nxp,sja1105q";
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- spi-max-frequency = <1000000>;
- spi-rx-delay-us = <1>;
- spi-tx-delay-us = <1>;
- spi-cpha;
-
- reset-gpios = <&gpioi 0 GPIO_ACTIVE_LOW>;
-
- clocks = <&clock_sja1105>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "t10";
- phy-mode = "rgmii-id";
- phy-handle = <&t1_phy0>;
- };
-
- port@1 {
- reg = <1>;
- label = "t11";
- phy-mode = "rgmii-id";
- phy-handle = <&t1_phy1>;
- };
-
- port@2 {
- reg = <2>;
- label = "t12";
- phy-mode = "rgmii-id";
- phy-handle = <&t1_phy2>;
- };
-
- port@3 {
- reg = <3>;
- label = "t13";
- phy-mode = "rgmii-id";
- phy-handle = <&t1_phy3>;
- };
-
- port@4 {
- reg = <4>;
- label = "cpu";
- ethernet = <ðernet0>;
- phy-mode = "rgmii-id";
- rx-internal-delay-ps = <2000>;
- tx-internal-delay-ps = <2000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
-};
-
-&usbotg_hs {
- dr_mode = "host";
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- phys = <&usbphyc_port1 0>;
- phy-names = "usb2-phy";
- vbus-supply = <&v5v>;
- status = "okay";
-};
-
-&usbphyc {
- status = "okay";
-};
-
-&usbphyc_port1 {
- phy-supply = <&v3v3>;
-};
-
-&uart4 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart4_pins_a>;
- pinctrl-1 = <&uart4_sleep_pins_a>;
- pinctrl-2 = <&uart4_idle_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&pinctrl {
- ethernet0_rgmii_pins_x: rgmii-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('B', 13, AF11)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('B', 8, AF11)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
- bias-disable;
- };
- };
-
- ethernet0_rgmii_sleep_pins_x: rgmii-sleep-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('B', 13, ANALOG)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('B', 8, ANALOG)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
- };
- };
-};
--
2.39.5
