This patch add support for additional bank info used by LPDDR5.
Taken from U-boot code, commit 875bc40 by YouMin Chen <cym@xxxxxxxxxxxxxx>
Signed-off-by: Alexander Shiyan <eagle.alexander923@xxxxxxxxx>
---
arch/arm/mach-rockchip/dmc.c | 7 ++++++-
include/mach/rockchip/dmc.h | 11 +++++++----
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-rockchip/dmc.c b/arch/arm/mach-rockchip/dmc.c
index 81c7e2649e..86e61f3116 100644
--- a/arch/arm/mach-rockchip/dmc.c
+++ b/arch/arm/mach-rockchip/dmc.c
@@ -58,7 +58,12 @@ static resource_size_t rockchip_sdram_size(u32 sys_reg2, u32 sys_reg3)
cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
cs1_col = cs0_col;
- bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
+ if (dram_type == LPDDR5)
+ /* LPDDR5: 0:8bank(bk=3), 1:16bank(bk=4) */
+ bk = 3 + ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
+ else
+ /* Other: 0:8bank(bk=3), 1:4bank(bk=2) */
+ bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
cs0_row = sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & SYS_REG_CS0_ROW_MASK;
cs1_row = sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK;
diff --git a/include/mach/rockchip/dmc.h b/include/mach/rockchip/dmc.h
index ed256f6daf..3df9aa5e9c 100644
--- a/include/mach/rockchip/dmc.h
+++ b/include/mach/rockchip/dmc.h
@@ -12,10 +12,13 @@
enum {
DDR4 = 0,
- DDR3 = 0x3,
- LPDDR2 = 0x5,
- LPDDR3 = 0x6,
- LPDDR4 = 0x7,
+ DDR3 = 3,
+ LPDDR2 = 5,
+ LPDDR3 = 6,
+ LPDDR4 = 7,
+ LPDDR4X = 8,
+ LPDDR5 = 9,
+ DDR5 = 10,
UNUSED = 0xFF
};
--
2.38.2
