The NS16550 on the OMAP SoCs has a special mode register that contains a
disable bit. In order to use the peripheral, this bit needs to be
cleared.
We do that in ns16550_omap_init_port() and used to it for the DEBUG_LL
case in omap_uart_lowlevel_init().
Commit 89094b2a299b ("ARM: omap: Use ns16550 debug_ll helper") removed
this mode register write for the DEBUG_LL case, thereby rendering
DEBUG_LL on the BeagleBone Black non-functional.
Add back the missing register write to fix this.
This has not been tested on AM6xx, but the barebox proper driver also
writes a zero (after writing 0x80), so it's assumed that this write
would be a no-op there, because either the POR default or a previous
boot stage does already configure the peripheral this way.
Fixes: 89094b2a299b ("ARM: omap: Use ns16550 debug_ll helper")
Reported-by: Konstantin Kletschke <konstantin.kletschke@xxxxxxxxxxxxx>
Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
---
include/debug_ll/ns16550.h | 1 +
include/mach/omap/debug_ll.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/include/debug_ll/ns16550.h b/include/debug_ll/ns16550.h
index 2bad7a43ca91..64cb9cd102df 100644
--- a/include/debug_ll/ns16550.h
+++ b/include/debug_ll/ns16550.h
@@ -19,6 +19,7 @@
#define NS16550_LCR 0x3
#define NS16550_MCR 0x4
#define NS16550_LSR 0x5
+#define NS16550_MDR 0x8 /* TI OMAP Mode register */
#define NS16550_LCR_VAL 0x3 /* 8 data, 1 stop, no parity */
#define NS16550_MCR_VAL 0x3 /* RTS/DTR */
diff --git a/include/mach/omap/debug_ll.h b/include/mach/omap/debug_ll.h
index b0650abf2daa..a95c1bf140ac 100644
--- a/include/mach/omap/debug_ll.h
+++ b/include/mach/omap/debug_ll.h
@@ -57,6 +57,7 @@ static inline void omap_debug_ll_init(void)
divisor = debug_ll_ns16550_calc_divisor(48000000);
debug_ll_ns16550_init(base, divisor);
+ debug_ll_write_reg(base, NS16550_MDR, 0);
}
static inline void PUTC_LL(int c)
--
2.39.5
