On 26.09.24 15:14, Sascha Hauer wrote: > This is a combination of Linux commits: > > 6e69052f01d91 ("clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568") > ff3187eabb5ce ("clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568") > > These are needed for proper HDMI clock settings on RK3568. > > Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> Reviewed-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx> > --- > drivers/clk/rockchip/clk-rk3568.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c > index 50fbf66d23..bd6c8269ca 100644 > --- a/drivers/clk/rockchip/clk-rk3568.c > +++ b/drivers/clk/rockchip/clk-rk3568.c > @@ -1050,13 +1050,13 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { > RK3568_CLKGATE_CON(20), 8, GFLAGS), > GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0, > RK3568_CLKGATE_CON(20), 9, GFLAGS), > - COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, > + COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, > RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS, > RK3568_CLKGATE_CON(20), 10, GFLAGS), > - COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, > + COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, > RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS, > RK3568_CLKGATE_CON(20), 11, GFLAGS), > - COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0, > + COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, > RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS, > RK3568_CLKGATE_CON(20), 12, GFLAGS), > GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0, > @@ -1574,7 +1574,7 @@ static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = { > RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS), > GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0, > RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS), > - MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0, > + MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT, > RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS), > }; > > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |