Adoption of Linux commit: | commit c5a8045a553e32529ffb6bfb33fcad4d38aec2c7 | Author: Emil Lundmark <emil@xxxxxxxxxxxxxx> | Date: Wed Oct 12 12:31:41 2016 +0200 | | clk: imx: improve precision of AV PLL to 1 Hz | | The audio and video PLLs are designed to have a precision of 1 Hz if some | conditions are met. The current implementation only allows a precision that | depends on the rate of the parent clock. E.g., if the parent clock is 24 | MHz, the precision will be 24 Hz; or more generally the precision will be | | p / 10^6 Hz | | where p is the parent clock rate. This comes down to how the register | values for the PLL's fractional loop divider are chosen. | | The clock rate calculation for the PLL is | | PLL output frequency = Fref * (DIV_SELECT + NUM / DENOM) | | or with a shorter notation | | r = p * (d + a / b) | | In addition to all variables being integers, we also have the following | conditions: | | 27 <= d <= 54 | | -2^29 <= a <= 2^29-1 | 0 < b <= 2^30-1 | |a| < b | | Here, d, a and b are register values for the fractional loop divider. We | want to chose d, a and b such that f(p, r) = p, i.e. f is our round_rate | function. Currently, d and b are chosen as | | d = r / p | b = 10^6 | | hence we get the poor precision. And a is defined in terms of r, d, p and | b: | | a = (r - d * p) * b / p | | I propose that if p <= 2^30-1 (i.e., the max value for b), we chose b as | | b = p | | We can do this since | | |a| < b | | |(r - d * p) * b / p| < b | | |r - d * p| < p | | Which have two solutions, one of them is when p < 0, so we can skip that | one. The other is when p > 0 and | | p * (d - 1) < r < p * (d + 1) | | Substitute d = r / p: | | (r - p) < r < (r + p) <=> p > 0 | | So, as long as p > 0, we can chose b = p. This is a good choise for b since | | a = (r - d * p) * b / p | = (r - d * p) * p / p | = r - d * p | | r = p * (d + a / b) | = p * d + p * a / b | = p * d + p * a / p | = p * d + a | | and if d = r / p: | | a = r - d * p | = r - r / p * p | = 0 | | r = p * d + a | = p * d + 0 | = p * r / p | = r | | I reckon this is the intention by the design of the clock rate formula. | | Signed-off-by: Emil Lundmark <emil@xxxxxxxxxxxxxx> | Reviewed-by: Fabio Estevam <fabio.estevam@xxxxxxx> | Acked-by: Shawn Guo <shawnguo@xxxxxxxxxx> | Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx> This patch helps getting the correct frequency out of the HDMI clock on an i.MX6. Without it it happens that the PLL sets a frequency that is a few HZ too high. A clk_set_rate() on the HDMI clock then increases the divider value to the next value because the resulting frequency would also be a few HZ too high otherwise. Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> --- drivers/clk/imx/clk-pllv3.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index cb1d65058f..eb806e7f98 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -203,6 +203,7 @@ static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long max_rate = parent_rate * 54; u32 div; u32 mfn, mfd = 1000000; + u32 max_mfd = 0x3FFFFFFF; u64 temp64; if (rate > max_rate) @@ -210,6 +211,9 @@ static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, else if (rate < min_rate) rate = min_rate; + if (parent_rate <= max_mfd) + mfd = parent_rate; + div = rate / parent_rate; temp64 = (u64) (rate - div * parent_rate); temp64 *= mfd; @@ -228,11 +232,15 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long max_rate = parent_rate * 54; u32 val, div; u32 mfn, mfd = 1000000; + u32 max_mfd = 0x3FFFFFFF; u64 temp64; if (rate < min_rate || rate > max_rate) return -EINVAL; + if (parent_rate <= max_mfd) + mfd = parent_rate; + div = rate / parent_rate; temp64 = (u64) (rate - div * parent_rate); temp64 *= mfd; -- 2.39.5
