Currently we don't honor the setup done by the BootROM. Fix this by reading the scr_el3 first and update the corresponding bits afterwards. Furthermore also align the register settings: - Remove the register with (RW) setup since this is done by the EL3 firmware (TF-A). - Set IRQ/FIQ/EA bits to make it possible to handle early exceptions within the PBL at EL3. Early exception handling requires platform support since it involves exception table and DAIF handling. Signed-off-by: Marco Felsch <m.felsch@xxxxxxxxxxxxxx> --- v2: - adapt the commit message arch/arm/cpu/lowlevel_64.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/lowlevel_64.S b/arch/arm/cpu/lowlevel_64.S index ed00c8c47057..dc76a9fcdac5 100644 --- a/arch/arm/cpu/lowlevel_64.S +++ b/arch/arm/cpu/lowlevel_64.S @@ -10,8 +10,8 @@ ENTRY(arm_cpu_lowlevel_init) switch_el x1, 3f, 2f, 1f 3: - mov x0, #1 /* Non-Secure EL0/1 */ - orr x0, x0, #(1 << 10) /* 64-bit EL2 */ + mrs x0, scr_el3 + orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */ msr scr_el3, x0 msr cptr_el3, xzr -- 2.39.2
