The i.MX27 USB ports have device tree support, so switch the board
over to use it. We still need to do some board specific setup to reset
the ULPI phys properly, so there's still some board code needed.
Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
---
arch/arm/boards/phytec-phycard-imx27/pca100.c | 92 ++++++++-----------
.../arm/dts/imx27-phytec-phycard-s-rdk-bb.dts | 1 +
arch/arm/dts/imx27-phytec-phycard-s-som.dtsi | 50 ++++++++++
3 files changed, 89 insertions(+), 54 deletions(-)
create mode 100644 arch/arm/dts/imx27-phytec-phycard-s-som.dtsi
diff --git a/arch/arm/boards/phytec-phycard-imx27/pca100.c b/arch/arm/boards/phytec-phycard-imx27/pca100.c
index 6a881498c2..011f9b9d11 100644
--- a/arch/arm/boards/phytec-phycard-imx27/pca100.c
+++ b/arch/arm/boards/phytec-phycard-imx27/pca100.c
@@ -24,30 +24,39 @@
#include <mach/imx/bbu.h>
#include <mach/imx/iomux-mx27.h>
-#if defined(CONFIG_USB) && defined(CONFIG_USB_ULPI)
-static void pca100_usb_register(void)
-{
- mdelay(10);
-
- gpio_direction_output(GPIO_PORTB + 24, 0);
- gpio_direction_output(GPIO_PORTB + 23, 0);
-
- mdelay(10);
-
- ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x170), 1);
- add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR, NULL);
- ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1);
- add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL);
-}
-#else
-static void pca100_usb_register(void) { };
-#endif
-
static void pca100_usb_init(void)
{
struct device_node *gpio_np;
u32 reg;
int ret;
+ int i;
+ unsigned int mode[] = {
+ /* USB host 2 */
+ PA0_PF_USBH2_CLK,
+ PA1_PF_USBH2_DIR,
+ PA2_PF_USBH2_DATA7,
+ PA3_PF_USBH2_NXT,
+ PA4_PF_USBH2_STP,
+ PD19_AF_USBH2_DATA4,
+ PD20_AF_USBH2_DATA3,
+ PD21_AF_USBH2_DATA6,
+ PD22_AF_USBH2_DATA0,
+ PD23_AF_USBH2_DATA2,
+ PD24_AF_USBH2_DATA1,
+ PD26_AF_USBH2_DATA5,
+ PC7_PF_USBOTG_DATA5,
+ PC8_PF_USBOTG_DATA6,
+ PC9_PF_USBOTG_DATA0,
+ PC10_PF_USBOTG_DATA2,
+ PC11_PF_USBOTG_DATA1,
+ PC12_PF_USBOTG_DATA4,
+ PC13_PF_USBOTG_DATA3,
+ PE0_PF_USBOTG_NXT,
+ PE1_PF_USBOTG_STP,
+ PE2_PF_USBOTG_DIR,
+ PE24_PF_USBOTG_CLK,
+ PE25_PF_USBOTG_DATA7,
+ };
gpio_np = of_find_node_by_name_address(NULL, "gpio@10015100");
if (!gpio_np)
@@ -83,50 +92,25 @@ static void pca100_usb_init(void)
gpio_direction_output(GPIO_PORTB + 23, 1);
imx27_gpio_mode((GPIO_PORTB | 24) | GPIO_GPIO | GPIO_IN);
gpio_direction_output(GPIO_PORTB + 24, 1);
+
+ /* initizalize gpios */
+ for (i = 0; i < ARRAY_SIZE(mode); i++)
+ imx27_gpio_mode(mode[i]);
+
+ mdelay(10);
+
+ gpio_direction_output(GPIO_PORTB + 24, 0);
+ gpio_direction_output(GPIO_PORTB + 23, 0);
+
}
static int pca100_probe(struct device *dev)
{
- int i;
- unsigned int mode[] = {
- /* USB host 2 */
- PA0_PF_USBH2_CLK,
- PA1_PF_USBH2_DIR,
- PA2_PF_USBH2_DATA7,
- PA3_PF_USBH2_NXT,
- PA4_PF_USBH2_STP,
- PD19_AF_USBH2_DATA4,
- PD20_AF_USBH2_DATA3,
- PD21_AF_USBH2_DATA6,
- PD22_AF_USBH2_DATA0,
- PD23_AF_USBH2_DATA2,
- PD24_AF_USBH2_DATA1,
- PD26_AF_USBH2_DATA5,
- PC7_PF_USBOTG_DATA5,
- PC8_PF_USBOTG_DATA6,
- PC9_PF_USBOTG_DATA0,
- PC10_PF_USBOTG_DATA2,
- PC11_PF_USBOTG_DATA1,
- PC12_PF_USBOTG_DATA4,
- PC13_PF_USBOTG_DATA3,
- PE0_PF_USBOTG_NXT,
- PE1_PF_USBOTG_STP,
- PE2_PF_USBOTG_DIR,
- PE24_PF_USBOTG_CLK,
- PE25_PF_USBOTG_DATA7,
- };
-
barebox_set_model("Phytec phyCARD-i.MX27");
barebox_set_hostname("phycard-imx27");
pca100_usb_init();
- /* initizalize gpios */
- for (i = 0; i < ARRAY_SIZE(mode); i++)
- imx27_gpio_mode(mode[i]);
-
- pca100_usb_register();
-
imx_bbu_external_nand_register_handler("nand", "/dev/nand0.boot",
BBU_HANDLER_FLAG_DEFAULT);
diff --git a/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts b/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts
index d9ba6abae6..b082bf4554 100644
--- a/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts
+++ b/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts
@@ -3,6 +3,7 @@
*/
#include <arm/nxp/imx/imx27-phytec-phycard-s-rdk.dts>
+#include "imx27-phytec-phycard-s-som.dtsi"
/ {
chosen {
diff --git a/arch/arm/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/dts/imx27-phytec-phycard-s-som.dtsi
new file mode 100644
index 0000000000..6bf467f7bf
--- /dev/null
+++ b/arch/arm/dts/imx27-phytec-phycard-s-som.dtsi
@@ -0,0 +1,50 @@
+
+&iomuxc {
+ imx27-phycard-s-som {
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
+ MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
+ MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
+ MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
+ MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
+ MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
+ MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
+ MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
+ MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
+ MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
+ MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
+ MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
+ >;
+ };
+
+ pinctrl_usbh2: usbh2grp {
+ fsl,pins = <
+ MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
+ MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
+ MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
+ MX27_PAD_USBH2_STP__USBH2_STP 0x0
+ MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
+ MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
+ MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
+ MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
+ MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
+ MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
+ MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
+ MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
+ >;
+ };
+ };
+};
+
+&usbh2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh2>;
+ phy_type = "ulpi";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ phy_type = "ulpi";
+};
--
2.39.2
