Am Freitag, dem 19.04.2024 um 08:13 +0200 schrieb Ahmad Fatoum:
> Unlike the i.MX8MM and i.MX8MN SoCs added earlier, the device tree for
> the i.MX8MP configures some clocks at frequencies that are only
> validated for overdrive mode, i.e. when VDD_SOC is 950 mV.
>
> Boards may want to run their SoC at the lower voltage of 850 mV though
> to reduce heat generation and power usage. For this to work, clock rates
> need to adhere to the limits of the nominal drive mode.
>
> Add an optional DTSI file which can be included by various boards to run
> in this mode.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
> ---
> arch/arm/dts/imx8mp-nominal.dtsi | 51 ++++++++++++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
> create mode 100644 arch/arm/dts/imx8mp-nominal.dtsi
>
> diff --git a/arch/arm/dts/imx8mp-nominal.dtsi b/arch/arm/dts/imx8mp-nominal.dtsi
> new file mode 100644
> index 000000000000..a9f46503f656
> --- /dev/null
> +++ b/arch/arm/dts/imx8mp-nominal.dtsi
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +&clk {
> + assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
> + <&clk IMX8MP_CLK_A53_CORE>,
> + <&clk IMX8MP_SYS_PLL3>,
> + <&clk IMX8MP_CLK_NOC>,
> + <&clk IMX8MP_CLK_NOC_IO>,
> + <&clk IMX8MP_CLK_GIC>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
> + <&clk IMX8MP_ARM_PLL_OUT>,
> + <0>,
> + <&clk IMX8MP_SYS_PLL1_800M>,
> + <&clk IMX8MP_SYS_PLL3_OUT>,
> + <&clk IMX8MP_SYS_PLL1_800M>;
> + assigned-clock-rates = <0>, <0>,
> + <600000000>,
> + <800000000>,
> + <600000000>,
> + <400000000>;
> +};
> +
> +&pgc_hsiomix {
> + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
> + assigned-clock-rates = <400000000>;
> +};
> +
> +&pgc_gpumix {
> + assigned-clocks = <&clk IMX8MP_GPU_PLL>,
> + <&clk IMX8MP_CLK_GPU_AXI>,
> + <&clk IMX8MP_CLK_GPU_AHB>;
> + assigned-clock-parents = <0>,
> + <&clk IMX8MP_GPU_PLL_OUT>,
> + <&clk IMX8MP_GPU_PLL_OUT>;
> + assigned-clock-rates = <600000000>, <600000000>, <300000000>;
Use SYS_PLL3 as the parent clock, instead of GPU PLL.
> +};
> +
> +&media_blk_ctrl {
> + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
> + <&clk IMX8MP_CLK_MEDIA_APB>,
> + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
> + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
> + <&clk IMX8MP_VIDEO_PLL1>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
> + <&clk IMX8MP_SYS_PLL1_800M>,
> + <&clk IMX8MP_VIDEO_PLL1_OUT>,
> + <&clk IMX8MP_VIDEO_PLL1_OUT>;
> + assigned-clock-rates = <400000000>, <200000000>,
> + <0>, <0>, <1039500000>;
> +};
