On Tue, 02 Apr 2024 15:44:59 +0200, Ahmad Fatoum wrote:
> The StarFive SoCs are 64-bit, but the L2 cache driver could be
> compile-tested on 32-bit as well. Currently, this would fail, because
> writeq isn't defined. Fix this by emulating it using a lo-hi write.
>
>
Applied, thanks!
[1/3] soc: sifive: l2_cache: fix 32-bit compilation
https://git.pengutronix.de/cgit/barebox/commit/?id=046ceb972493 (link may not be stable)
[2/3] RISC-V: riscvemu: build overlay as DTSO
https://git.pengutronix.de/cgit/barebox/commit/?id=d75ee46bea16 (link may not be stable)
[3/3] treewide: replace references to barebox.org/jsbarebox with demo
https://git.pengutronix.de/cgit/barebox/commit/?id=c0dde74b1c9a (link may not be stable)
Best regards,
--
Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
