To work around an erratum, the previous booting stage may have increased the
amount of rows to fake having 4G of RAM. In that case, we assume the previous
booting stage will have fixed up a proper memory size into the device tree and
don't use the calculated dram size. The erratum itself appears to be
undocumented by Altera/Intel and the workaround was introduced in the Alteras
fork of U-Boot back in 2014 and ported to mainline later, the linked FogBugz
issue is unfortunately not accessible.
[1] github.com/altera-opensource/u-boot-socfpga/commit/93815696dce132ff8abc4ab2f4c195339ff821a0
Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
Signed-off-by: Stefan Kerkmann <s.kerkmann@xxxxxxxxxxxxxx>
---
To work around an erratum in the Altera DRAM controller, the previous
booting stage may have increased the amount of rows to fake having 4G of
RAM. In that case, we assume the previous booting stage will have fixed
up a proper memory size into the device tree and don't use the
calculated dram size. The erratum itself appears to be undocumented by
Altera/Intel and the workaround was introduced in the Alteras fork of
U-Boot back in 2014 and ported to mainline later, the linked FogBugz
issue is unfortunately not accessible.
[1] github.com/altera-opensource/u-boot-socfpga/commit/93815696dce132ff8abc4ab2f4c195339ff821a0
---
arch/arm/mach-socfpga/cyclone5-generic.c | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-socfpga/cyclone5-generic.c b/arch/arm/mach-socfpga/cyclone5-generic.c
index ae8142b31c..0cb46b51e9 100644
--- a/arch/arm/mach-socfpga/cyclone5-generic.c
+++ b/arch/arm/mach-socfpga/cyclone5-generic.c
@@ -128,7 +128,8 @@ void socfpga_cyclone5_timer_init(void)
static int socfpga_detect_sdram(void)
{
void __iomem *base = (void *)CYCLONE5_SDR_ADDRESS;
- uint32_t dramaddrw, ctrlwidth, memsize;
+ uint32_t dramaddrw, ctrlwidth;
+ uint64_t memsize;
int colbits, rowbits, bankbits;
int width_bytes;
@@ -153,12 +154,20 @@ static int socfpga_detect_sdram(void)
break;
}
- memsize = (1 << colbits) * (1 << rowbits) * (1 << bankbits) * width_bytes;
+ memsize = (1ULL << colbits) * (1ULL << rowbits) * (1ULL << bankbits) *
+ width_bytes;
- pr_debug("%s: colbits: %d rowbits: %d bankbits: %d width: %d => memsize: 0x%08x\n",
+ pr_debug(
+ "%s: colbits: %d rowbits: %d bankbits: %d width: %d => memsize: 0x%08llx\n",
__func__, colbits, rowbits, bankbits, width_bytes, memsize);
- arm_add_mem_device("ram0", 0x0, memsize);
+ /* To work around an erratum in the dram controller, the previous booting
+ * stage may have increased the amount of rows to fake having 4G of RAM. In
+ * that case, we assume the previous booting stage will have fixed up a
+ * proper memory size into the device tree and don't add a bank here */
+ if (memsize < SZ_4G) {
+ arm_add_mem_device("ram0", 0x0, memsize);
+ }
return 0;
}
---
base-commit: 975acf1bafba2366eb40c5e8d8cb732b53f27aa1
change-id: 20231214-fix-socfpga-dram-errata-workaround-66cae33d7eed
Best regards,
--
Stefan Kerkmann <s.kerkmann@xxxxxxxxxxxxxx>
