CM4 is quite different from the Rpi4, so we should really not use the
same DT for both. Rpi 400 is nearly the same, but has a different MDIO
clock, so let's ship a different DT for that as well. They are
compressed anyway and the FAT partition should be big enough to handle a
few extra tens of kilobytes.
Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
---
arch/arm/boards/raspberry-pi/lowlevel.c | 8 ++++++--
arch/arm/dts/Makefile | 2 +-
arch/arm/dts/bcm2711-rpi-4.dts | 15 +++------------
arch/arm/dts/bcm2711-rpi-400.dts | 4 ++++
arch/arm/dts/bcm2711-rpi-cm4-io.dts | 4 ++++
arch/arm/dts/bcm2711-rpi.dtsi | 13 +++++++++++++
6 files changed, 31 insertions(+), 15 deletions(-)
create mode 100644 arch/arm/dts/bcm2711-rpi-400.dts
create mode 100644 arch/arm/dts/bcm2711-rpi-cm4-io.dts
create mode 100644 arch/arm/dts/bcm2711-rpi.dtsi
diff --git a/arch/arm/boards/raspberry-pi/lowlevel.c b/arch/arm/boards/raspberry-pi/lowlevel.c
index f8078dba677c..a1e195d81151 100644
--- a/arch/arm/boards/raspberry-pi/lowlevel.c
+++ b/arch/arm/boards/raspberry-pi/lowlevel.c
@@ -71,6 +71,8 @@ extern char __dtb_z_bcm2836_rpi_2_start[];
extern char __dtb_z_bcm2837_rpi_3_start[];
extern char __dtb_z_bcm2837_rpi_cm3_start[];
extern char __dtb_z_bcm2711_rpi_4_start[];
+extern char __dtb_z_bcm2711_rpi_400_start[];
+extern char __dtb_z_bcm2711_rpi_cm4_io_start[];
RPI_ENTRY_FUNCTION(start_raspberry_pi1, SZ_128M, fdt)
{
@@ -132,9 +134,11 @@ static void *rpi_get_board_fdt(int rev)
return DT_IF_ENABLED(__dtb_z_bcm2837_rpi_cm3_start, CONFIG_MACH_RPI_CM3);
case BCM2711_BOARD_REV_4_B:
- case BCM2711_BOARD_REV_400:
- case BCM2711_BOARD_REV_CM4:
return DT_IF_ENABLED(__dtb_z_bcm2711_rpi_4_start, CONFIG_MACH_RPI4);
+ case BCM2711_BOARD_REV_400:
+ return DT_IF_ENABLED(__dtb_z_bcm2711_rpi_400_start, CONFIG_MACH_RPI4);
+ case BCM2711_BOARD_REV_CM4:
+ return DT_IF_ENABLED(__dtb_z_bcm2711_rpi_cm4_io_start, CONFIG_MACH_RPI4);
}
return NULL;
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 4d837b13411c..04af3bd64687 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -123,7 +123,7 @@ lwl-$(CONFIG_MACH_RPI) += bcm2835-rpi.dtb.o
lwl-$(CONFIG_MACH_RPI2) += bcm2836-rpi-2.dtb.o
lwl-$(CONFIG_MACH_RPI3) += bcm2837-rpi-3.dtb.o
lwl-$(CONFIG_MACH_RPI_CM3) += bcm2837-rpi-cm3.dtb.o
-lwl-$(CONFIG_MACH_RPI4) += bcm2711-rpi-4.dtb.o
+lwl-$(CONFIG_MACH_RPI4) += bcm2711-rpi-4.dtb.o bcm2711-rpi-400.dtb.o bcm2711-rpi-cm4-io.dtb.o
lwl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o
lwl-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o imx6qp-sabresd.dtb.o
lwl-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o
diff --git a/arch/arm/dts/bcm2711-rpi-4.dts b/arch/arm/dts/bcm2711-rpi-4.dts
index de748e2fc65b..6d46dd3b839c 100644
--- a/arch/arm/dts/bcm2711-rpi-4.dts
+++ b/arch/arm/dts/bcm2711-rpi-4.dts
@@ -1,13 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
+
#include <arm64/broadcom/bcm2711-rpi-4-b.dts>
-
-&{/memory@0} {
- reg = <0x0 0x0 0x0>;
-};
-
-&uart1 {
- /* VPU core clock is reported at 200MHz, but needs to be 500Mhz
- * for ns16550 driver to set correct baudrate. Until that's
- * figured out, hardcode clock frequency to the expected value
- */
- clock-frequency = <500000000>;
-};
+#include "bcm2711-rpi.dtsi"
diff --git a/arch/arm/dts/bcm2711-rpi-400.dts b/arch/arm/dts/bcm2711-rpi-400.dts
new file mode 100644
index 000000000000..fb9cccb2b914
--- /dev/null
+++ b/arch/arm/dts/bcm2711-rpi-400.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <arm64/broadcom/bcm2711-rpi-400.dts>
+#include "bcm2711-rpi.dtsi"
diff --git a/arch/arm/dts/bcm2711-rpi-cm4-io.dts b/arch/arm/dts/bcm2711-rpi-cm4-io.dts
new file mode 100644
index 000000000000..115491e7a638
--- /dev/null
+++ b/arch/arm/dts/bcm2711-rpi-cm4-io.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <arm64/broadcom/bcm2711-rpi-cm4-io.dts>
+#include "bcm2711-rpi.dtsi"
diff --git a/arch/arm/dts/bcm2711-rpi.dtsi b/arch/arm/dts/bcm2711-rpi.dtsi
new file mode 100644
index 000000000000..cb2952ccac85
--- /dev/null
+++ b/arch/arm/dts/bcm2711-rpi.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+
+&{/memory@0} {
+ reg = <0x0 0x0 0x0>;
+};
+
+&uart1 {
+ /* VPU core clock is reported at 200MHz, but needs to be 500Mhz
+ * for ns16550 driver to set correct baudrate. Until that's
+ * figured out, hardcode clock frequency to the expected value
+ */
+ clock-frequency = <500000000>;
+};
--
2.39.2
