We already support CLK_DIVIDER_ONE_BASED and incoming STM32MP13 clock
support can have clock dividers evaluate to zero. Add support for
CLK_DIVIDER_ALLOW_ZERO analogously to Linux.
Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
---
drivers/clk/clk-divider.c | 6 ++++++
include/linux/clk.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 1eaff1675b24..150b1fe60fd4 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -88,6 +88,12 @@ unsigned long divider_recalc_rate(struct clk *clk, unsigned long parent_rate,
unsigned int div;
div = _get_div(table, val, flags, width);
+ if (!div) {
+ WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
+ "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
+ clk->name);
+ return parent_rate;
+ }
return DIV_ROUND_UP_ULL((u64)parent_rate, div);
}
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 9975c1a601c4..269664b0ba63 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -417,6 +417,7 @@ struct clk_divider {
#define clk_div_mask(width) ((1 << (width)) - 1)
#define CLK_DIVIDER_POWER_OF_TWO (1 << 1)
+#define CLK_DIVIDER_ALLOW_ZERO (1 << 2)
#define CLK_DIVIDER_HIWORD_MASK (1 << 3)
#define CLK_DIVIDER_READ_ONLY (1 << 5)
--
2.39.2
