On the Debix SBC the EQOS interface is used as primary interface, the FEC pins are routed to the extension header. On the other hand the Debix SoM/Baseboard combination both interfaces are used. So fix the RGMII pin setup by adding the EQOS pin as well and keep the FEC. Signed-off-by: Marco Felsch <m.felsch@xxxxxxxxxxxxxx> --- arch/arm/boards/polyhex-debix/board.c | 3 ++- include/mach/imx/iomux-mx8mp.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boards/polyhex-debix/board.c b/arch/arm/boards/polyhex-debix/board.c index d668dd1816f8..46cb18c5889c 100644 --- a/arch/arm/boards/polyhex-debix/board.c +++ b/arch/arm/boards/polyhex-debix/board.c @@ -28,7 +28,8 @@ static int polyhex_debix_probe(struct device *dev) /* Enable RGMII TX clk output */ val = readl(MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1); - val |= MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN; + val |= MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN | + MX8MP_IOMUXC_GPR1_ENET_QOS_RGMII_EN; writel(val, MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1); return 0; diff --git a/include/mach/imx/iomux-mx8mp.h b/include/mach/imx/iomux-mx8mp.h index b410eaebc8ac..98e340d3dad1 100644 --- a/include/mach/imx/iomux-mx8mp.h +++ b/include/mach/imx/iomux-mx8mp.h @@ -1099,5 +1099,6 @@ static inline void imx8mp_setup_pad(iomux_v3_cfg_t pad) #define MX8MP_IOMUXC_GPR1 0x4 #define MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN BIT(22) +#define MX8MP_IOMUXC_GPR1_ENET_QOS_RGMII_EN BIT(21) #endif /* __ASM_ARCH_IMX8MP_PINS_H__ */ -- 2.39.2
