From: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
Update to new DDR3 calibration values. The values are taken from the
NXP DDR Stress Test (3.0.0) on a board variant 24 (ptx internal
inventory skov-K-00-04624).
The DRAM controller settings and IOMUX settings have been taken from
the MX6DQ_DDR3_register_programming_aid_v2.4.xlxs file.
DDR setup debug output:
-----------------------
density:8 Gb (2 Gb per chip)
clock: 528MHz (1893 ps)
memspd:1066
tcke=2
tcksrx=6
tcksre=6
taofpd=1
taonpd=1
todtlon=4
tanpd=4
taxpd=4
trfc=84
txs=89
txp=3
txpdll=12
tfaw=26
tcl=5
trcd=7
trp=7
trc=25
tras=18
twr=7
tmrd=11
tcwl=4
tdllk=511
trtp=3
twtr=3
trrd=5
txpr=89
cs0_end=39
ncs=1
Rtt_wr=0
Rtt_nom=2
SRT=0
tcl=5
twr=7
MR2 CS0: 0x00088032
MR3 CS0: 0x00008033
MR1 CS0: 0x00408031
MR0 CS0: 0x19408030
============================================
DDR Stress Test (3.0.0)
Build: Dec 14 2018, 14:20:05
NXP Semiconductors.
============================================
============================================
Chip ID
CHIP ID = i.MX6 Dual/Quad (0x63)
Internal Revision = TO1.6
============================================
============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x28003032
SRC_SBMR2(0x020d801c) = 0x02000001
============================================
What ARM core speed would you like to run?
Type 1 for 800MHz, 2 for 1GHz, 3 for 1.2GHz
ARM Clock set to 800MHz
============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 14, col size: 10
Chip select CSD0 is used
Density per chip select: 1024MB
============================================
Current Temperature: 37
============================================
Please select the DDR density per chip select (in bytes) on the board
Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6 for 32MB
For maximum supported density (4GB), we can only access up to 3.75GB. Type 7 to select this
DDR density selected (MB): 128
Would do you want to change VDD_SOC_CAP/VDD_ARM_CAP voltage? Type 'y' to run and 'n' to skip
Would do you want run DDR Calibration? Type 'y' to run and 'n' to skip
Calibration will run at DDR frequency 528MHz. Type 'y' to continue.
If you want to run at other DDR frequency. Type 'n'
Please enter the MR1 value on the initilization script
This will be re-programmed into MR1 after write leveling calibration
Enter as a 4-digit HEX value, example 0004, then hit enter
0040DDR Freq: 528 MHz
ddr_mr1=0x00000040
Start write leveling calibration...
running Write level HW calibration
MPWLHWERR register read out for factory diagnostics:
MPWLHWERR PHY0 = 0x3c3e3c3c
MPWLHWERR PHY1 = 0x3e3c3e3c
Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00230023
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x0029001E
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001F002A
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x001A0028
Write DQS delay result:
Write DQS0 delay: 35/256 CK
Write DQS1 delay: 35/256 CK
Write DQS2 delay: 30/256 CK
Write DQS3 delay: 41/256 CK
Write DQS4 delay: 42/256 CK
Write DQS5 delay: 31/256 CK
Write DQS6 delay: 40/256 CK
Write DQS7 delay: 26/256 CK
WARNING: write-leveling calibration value is greater than 1/8 CK.
Per the reference manual, WALAT must be set to 1 in the register MDMISC(0x021B0018).
This has been performed automatically.
However, in addition to updating the calibration values in your DDR initialization,
it is also REQUIRED change the value of MDMISC in their DDR initialization as follows:
MMDC_MDMISC (0x021b0018) = 0x00091740
Starting DQS gating calibration
. HC_DEL=0x00000000 result[00]=0x11101101
. HC_DEL=0x00000001 result[01]=0x11101101
. HC_DEL=0x00000002 result[02]=0x00100001
. HC_DEL=0x00000003 result[03]=0x00000000
. HC_DEL=0x00000004 result[04]=0x00000000
. HC_DEL=0x00000005 result[05]=0x11111111
. HC_DEL=0x00000006 result[06]=0x11111111
. HC_DEL=0x00000007 result[07]=0x11111111
. HC_DEL=0x00000008 result[08]=0x11111111
. HC_DEL=0x00000009 result[09]=0x11111111
. HC_DEL=0x0000000A result[0A]=0x11111111
. HC_DEL=0x0000000B result[0B]=0x11111111
. HC_DEL=0x0000000C result[0C]=0x11111111
. HC_DEL=0x0000000D result[0D]=0x11111111
DQS HC delay value low1 = 0x02020003, high1=0x04040404
DQS HC delay value low2 = 0x02020300, high2=0x04040404
loop ABS offset to get HW_DG_LOW
. ABS_OFFSET=0x00000000 result[00]=0x11101101
. ABS_OFFSET=0x00000004 result[01]=0x11101101
. ABS_OFFSET=0x00000008 result[02]=0x11001101
. ABS_OFFSET=0x0000000C result[03]=0x11011111
. ABS_OFFSET=0x00000010 result[04]=0x11001100
. ABS_OFFSET=0x00000014 result[05]=0x11001100
. ABS_OFFSET=0x00000018 result[06]=0x11001100
. ABS_OFFSET=0x0000001C result[07]=0x11001100
. ABS_OFFSET=0x00000020 result[08]=0x11001100
. ABS_OFFSET=0x00000024 result[09]=0x11001100
. ABS_OFFSET=0x00000028 result[0A]=0x11001100
. ABS_OFFSET=0x0000002C result[0B]=0x11001100
. ABS_OFFSET=0x00000030 result[0C]=0x11001100
. ABS_OFFSET=0x00000034 result[0D]=0x11001100
. ABS_OFFSET=0x00000038 result[0E]=0x11011110
. ABS_OFFSET=0x0000003C result[0F]=0x11001100
. ABS_OFFSET=0x00000040 result[10]=0x11001100
. ABS_OFFSET=0x00000044 result[11]=0x11011110
. ABS_OFFSET=0x00000048 result[12]=0x11001100
. ABS_OFFSET=0x0000004C result[13]=0x11001100
. ABS_OFFSET=0x00000050 result[14]=0x10001100
. ABS_OFFSET=0x00000054 result[15]=0x10001100
. ABS_OFFSET=0x00000058 result[16]=0x10001100
. ABS_OFFSET=0x0000005C result[17]=0x10001100
. ABS_OFFSET=0x00000060 result[18]=0x10001100
. ABS_OFFSET=0x00000064 result[19]=0x10010110
. ABS_OFFSET=0x00000068 result[1A]=0x00000100
. ABS_OFFSET=0x0000006C result[1B]=0x00000000
. ABS_OFFSET=0x00000070 result[1C]=0x00000000
. ABS_OFFSET=0x00000074 result[1D]=0x00000000
. ABS_OFFSET=0x00000078 result[1E]=0x00000000
. ABS_OFFSET=0x0000007C result[1F]=0x00000000
loop ABS offset to get HW_DG_HIGH
. ABS_OFFSET=0x00000000 result[00]=0x00000000
. ABS_OFFSET=0x00000004 result[01]=0x01000000
. ABS_OFFSET=0x00000008 result[02]=0x01000000
. ABS_OFFSET=0x0000000C result[03]=0x01000000
. ABS_OFFSET=0x00000010 result[04]=0x01000000
. ABS_OFFSET=0x00000014 result[05]=0x01000000
. ABS_OFFSET=0x00000018 result[06]=0x01000000
. ABS_OFFSET=0x0000001C result[07]=0x01000000
. ABS_OFFSET=0x00000020 result[08]=0x01000000
. ABS_OFFSET=0x00000024 result[09]=0x01000000
. ABS_OFFSET=0x00000028 result[0A]=0x01000000
. ABS_OFFSET=0x0000002C result[0B]=0x01000000
. ABS_OFFSET=0x00000030 result[0C]=0x01000000
. ABS_OFFSET=0x00000034 result[0D]=0x01100100
. ABS_OFFSET=0x00000038 result[0E]=0x11100100
. ABS_OFFSET=0x0000003C result[0F]=0x11101100
. ABS_OFFSET=0x00000040 result[10]=0x11101100
. ABS_OFFSET=0x00000044 result[11]=0x11111110
. ABS_OFFSET=0x00000048 result[12]=0x11111110
. ABS_OFFSET=0x0000004C result[13]=0x11111110
. ABS_OFFSET=0x00000050 result[14]=0x11111110
. ABS_OFFSET=0x00000054 result[15]=0x11111111
. ABS_OFFSET=0x00000058 result[16]=0x11111111
. ABS_OFFSET=0x0000005C result[17]=0x11111111
. ABS_OFFSET=0x00000060 result[18]=0x11111111
. ABS_OFFSET=0x00000064 result[19]=0x11111111
. ABS_OFFSET=0x00000068 result[1A]=0x11111111
. ABS_OFFSET=0x0000006C result[1B]=0x11111111
. ABS_OFFSET=0x00000070 result[1C]=0x11111111
. ABS_OFFSET=0x00000074 result[1D]=0x11111111
. ABS_OFFSET=0x00000078 result[1E]=0x11111111
. ABS_OFFSET=0x0000007C result[1F]=0x11111111
BYTE 0:
Start: HC=0x02 ABS=0x10
End: HC=0x04 ABS=0x50
Mean: HC=0x03 ABS=0x30
End-0.5*tCK: HC=0x03 ABS=0x50
Final: HC=0x03 ABS=0x50
BYTE 1:
Start: HC=0x00 ABS=0x00
End: HC=0x04 ABS=0x40
Mean: HC=0x02 ABS=0x20
End-0.5*tCK: HC=0x03 ABS=0x40
Final: HC=0x03 ABS=0x40
BYTE 2:
Start: HC=0x01 ABS=0x6C
End: HC=0x04 ABS=0x30
Mean: HC=0x03 ABS=0x0E
End-0.5*tCK: HC=0x03 ABS=0x30
Final: HC=0x03 ABS=0x30
BYTE 3:
Start: HC=0x01 ABS=0x64
End: HC=0x04 ABS=0x38
Mean: HC=0x03 ABS=0x0E
End-0.5*tCK: HC=0x03 ABS=0x38
Final: HC=0x03 ABS=0x38
BYTE 4:
Start: HC=0x00 ABS=0x00
End: HC=0x04 ABS=0x40
Mean: HC=0x02 ABS=0x20
End-0.5*tCK: HC=0x03 ABS=0x40
Final: HC=0x03 ABS=0x40
BYTE 5:
Start: HC=0x02 ABS=0x08
End: HC=0x04 ABS=0x30
Mean: HC=0x03 ABS=0x1C
End-0.5*tCK: HC=0x03 ABS=0x30
Final: HC=0x03 ABS=0x30
BYTE 6:
Start: HC=0x01 ABS=0x50
End: HC=0x04 ABS=0x00
Mean: HC=0x02 ABS=0x67
End-0.5*tCK: HC=0x03 ABS=0x00
Final: HC=0x03 ABS=0x00
BYTE 7:
Start: HC=0x01 ABS=0x68
End: HC=0x04 ABS=0x34
Mean: HC=0x03 ABS=0x0E
End-0.5*tCK: HC=0x03 ABS=0x34
Final: HC=0x03 ABS=0x34
DQS calibration MMDC0 MPDGCTRL0 = 0x43400350, MPDGCTRL1 = 0x03380330
DQS calibration MMDC1 MPDGCTRL0 = 0x43300340, MPDGCTRL1 = 0x03340300
Note: Array result[] holds the DRAM test result of each byte.
0: test pass. 1: test fail
4 bits respresent the result of 1 byte.
result 00000001:byte 0 fail.
result 00000011:byte 0, 1 fail.
Starting Read calibration...
ABS_OFFSET=0x00000000 result[00]=0x11111111
ABS_OFFSET=0x04040404 result[01]=0x11111111
ABS_OFFSET=0x08080808 result[02]=0x11111111
ABS_OFFSET=0x0C0C0C0C result[03]=0x11111111
ABS_OFFSET=0x10101010 result[04]=0x11011111
ABS_OFFSET=0x14141414 result[05]=0x01011001
ABS_OFFSET=0x18181818 result[06]=0x00011000
ABS_OFFSET=0x1C1C1C1C result[07]=0x00010000
ABS_OFFSET=0x20202020 result[08]=0x00000000
ABS_OFFSET=0x24242424 result[09]=0x00000000
ABS_OFFSET=0x28282828 result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
ABS_OFFSET=0x30303030 result[0C]=0x00000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
ABS_OFFSET=0x50505050 result[14]=0x00000000
ABS_OFFSET=0x54545454 result[15]=0x00000100
ABS_OFFSET=0x58585858 result[16]=0x00100100
ABS_OFFSET=0x5C5C5C5C result[17]=0x00100111
ABS_OFFSET=0x60606060 result[18]=0x11100111
ABS_OFFSET=0x64646464 result[19]=0x11101111
ABS_OFFSET=0x68686868 result[1A]=0x11110111
ABS_OFFSET=0x6C6C6C6C result[1B]=0x11111111
ABS_OFFSET=0x70707070 result[1C]=0x11111111
ABS_OFFSET=0x74747474 result[1D]=0x11111111
ABS_OFFSET=0x78787878 result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
Byte 0: (0x18 - 0x58), middle value:0x38
Byte 1: (0x14 - 0x58), middle value:0x36
Byte 2: (0x14 - 0x50), middle value:0x32
Byte 3: (0x1c - 0x60), middle value:0x3e
Byte 4: (0x20 - 0x64), middle value:0x42
Byte 5: (0x10 - 0x54), middle value:0x32
Byte 6: (0x18 - 0x5c), middle value:0x3a
Byte 7: (0x14 - 0x5c), middle value:0x38
MMDC0 MPRDDLCTL = 0x3E323638, MMDC1 MPRDDLCTL = 0x383A3242
Starting Write calibration...
ABS_OFFSET=0x00000000 result[00]=0x11111111
ABS_OFFSET=0x04040404 result[01]=0x10111111
ABS_OFFSET=0x08080808 result[02]=0x10110111
ABS_OFFSET=0x0C0C0C0C result[03]=0x10100010
ABS_OFFSET=0x10101010 result[04]=0x10100000
ABS_OFFSET=0x14141414 result[05]=0x00100000
ABS_OFFSET=0x18181818 result[06]=0x00000000
ABS_OFFSET=0x1C1C1C1C result[07]=0x00000000
ABS_OFFSET=0x20202020 result[08]=0x00000000
ABS_OFFSET=0x24242424 result[09]=0x00000000
ABS_OFFSET=0x28282828 result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
ABS_OFFSET=0x30303030 result[0C]=0x00000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
ABS_OFFSET=0x50505050 result[14]=0x00000000
ABS_OFFSET=0x54545454 result[15]=0x00000000
ABS_OFFSET=0x58585858 result[16]=0x00000000
ABS_OFFSET=0x5C5C5C5C result[17]=0x00000000
ABS_OFFSET=0x60606060 result[18]=0x00000000
ABS_OFFSET=0x64646464 result[19]=0x01000000
ABS_OFFSET=0x68686868 result[1A]=0x01000000
ABS_OFFSET=0x6C6C6C6C result[1B]=0x01011101
ABS_OFFSET=0x70707070 result[1C]=0x01011111
ABS_OFFSET=0x74747474 result[1D]=0x11011111
ABS_OFFSET=0x78787878 result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
Byte 0: (0x0c - 0x68), middle value:0x3a
Byte 1: (0x10 - 0x6c), middle value:0x3e
Byte 2: (0x0c - 0x68), middle value:0x3a
Byte 3: (0x08 - 0x68), middle value:0x38
Byte 4: (0x0c - 0x68), middle value:0x3a
Byte 5: (0x18 - 0x74), middle value:0x46
Byte 6: (0x04 - 0x60), middle value:0x32
Byte 7: (0x14 - 0x70), middle value:0x42
MMDC0 MPWRDLCTL = 0x383A3E3A,MMDC1 MPWRDLCTL = 0x4232463A
MMDC registers updated from calibration
Write leveling calibration
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00230023
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x0029001E
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001F002A
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x001A0028
Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x43400350
MPDGCTRL1 PHY0 (0x021b0840) = 0x03380330
MPDGCTRL0 PHY1 (0x021b483c) = 0x43300340
MPDGCTRL1 PHY1 (0x021b4840) = 0x03340300
Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x3E323638
MPRDDLCTL PHY1 (0x021b4848) = 0x383A3242
Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x383A3E3A
MPWRDLCTL PHY1 (0x021b4850) = 0x4232463A
Success: DDR calibration completed!!!
Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
---
arch/arm/boards/skov-imx6/lowlevel.c | 68 ++++++++++++++--------------
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git a/arch/arm/boards/skov-imx6/lowlevel.c b/arch/arm/boards/skov-imx6/lowlevel.c
index a7f5dce890ff..842e3af6db77 100644
--- a/arch/arm/boards/skov-imx6/lowlevel.c
+++ b/arch/arm/boards/skov-imx6/lowlevel.c
@@ -175,33 +175,33 @@ static const struct mx6_ddr_sysinfo skov_imx6_sysinfo_4x128Mb_1066MHz = {
.dsize = 2, /* 64 bit wide = 4 devices, 16 bit each */
.cs_density = 8, /* four 2 GBit devices connected */
.ncs = 1, /* one CS line for all devices */
- .cs1_mirror = 1, /* TODO */
- .bi_on = 1, /* TODO */
+ .cs1_mirror = 1,
+ .bi_on = 1,
.rtt_nom = 1, /* MX6_MMDC_P0_MPODTCTRL -> 0x00022227 */
.rtt_wr = 0, /* is LW_EN is 0 in their code */
- .ralat = 5, /* TODO */
- .walat = 1, /* TODO */
- .mif3_mode = 3, /* TODO */
- .rst_to_cke = 0x23, /* used in their code as well */
- .sde_to_rst = 0x10, /* used in their code as well */
- .pd_fast_exit = 0, /* TODO */
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+ .pd_fast_exit = 1,
};
/* calibration info for the "max performance" and "high performance" */
static const struct mx6_mmdc_calibration skov_imx6_calib_4x128Mb_1066MHz = {
- .p0_mpwldectrl0 = 0x0011000E,
- .p0_mpwldectrl1 = 0x000E001B,
- .p0_mpdgctrl0 = 0x42720306,
- .p0_mpdgctrl1 = 0x026F0266,
- .p0_mprddlctl = 0x45393B3E,
- .p0_mpwrdlctl = 0x40434541,
-
- .p1_mpwldectrl0 = 0x00190015,
- .p1_mpwldectrl1 = 0x00070018,
- .p1_mpdgctrl0 = 0x4273030A,
- .p1_mpdgctrl1 = 0x02740240,
- .p1_mprddlctl = 0x403A3747,
- .p1_mpwrdlctl = 0x473E4A3B,
+ .p0_mpwldectrl0 = 0x00230023,
+ .p0_mpwldectrl1 = 0x0029001E,
+ .p0_mpdgctrl0 = 0x43400350,
+ .p0_mpdgctrl1 = 0x03380330,
+ .p0_mprddlctl = 0x3E323638,
+ .p0_mpwrdlctl = 0x383A3E3A,
+
+ .p1_mpwldectrl0 = 0x001F002A,
+ .p1_mpwldectrl1 = 0x001A0028,
+ .p1_mpdgctrl0 = 0x43300340,
+ .p1_mpdgctrl1 = 0x03340300,
+ .p1_mprddlctl = 0x383A3242,
+ .p1_mpwrdlctl = 0x4232463A,
};
/* ------------------------------------------------------------------------ */
@@ -215,21 +215,21 @@ static struct mx6dq_iomux_ddr_regs ddr_iomux_q = {
.dram_sdqs5 = 0x00000030,
.dram_sdqs6 = 0x00000030,
.dram_sdqs7 = 0x00000030,
- .dram_dqm0 = 0x00020030,
- .dram_dqm1 = 0x00020030,
- .dram_dqm2 = 0x00020030,
- .dram_dqm3 = 0x00020030,
- .dram_dqm4 = 0x00020030,
- .dram_dqm5 = 0x00020030,
- .dram_dqm6 = 0x00020030,
- .dram_dqm7 = 0x00020030,
- .dram_cas = 0x00020030,
- .dram_ras = 0x00020030,
- .dram_sdclk_0 = 0x00020030,
- .dram_sdclk_1 = 0x00020030,
+ .dram_dqm0 = 0x00000030,
+ .dram_dqm1 = 0x00000030,
+ .dram_dqm2 = 0x00000030,
+ .dram_dqm3 = 0x00000030,
+ .dram_dqm4 = 0x00000030,
+ .dram_dqm5 = 0x00000030,
+ .dram_dqm6 = 0x00000030,
+ .dram_dqm7 = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_sdclk_0 = 0x00000030,
+ .dram_sdclk_1 = 0x00000030,
.dram_sdcke0 = 0x00003000,
.dram_sdcke1 = 0x00003000,
- .dram_reset = 0x00020030,
+ .dram_reset = 0x00000030,
.dram_sdba2 = 0x00000000,
.dram_sdodt0 = 0x00003030,
.dram_sdodt1 = 0x00003030,
--
2.39.2
