On Tue, Jun 27, 2023 at 05:42:00PM +0200, oss@xxxxxxxxx wrote:
> From: Jules Maselbas <jmaselbas@xxxxxxxxx>
>
> Since the rework of remap_range each architecture is expected to have
> the asm/mmu.h header, this wasn't the case for kvx, fix this.
>
> By default the KV3-1 cpu (as found in Coolidge SoC) starts with all memory
> uncached and MMU disabled. Data and instruction L1-caches are enabled very
> early during barebox start code, see arch/kvx/cpu/start.S, using the wfxl
> instruction to modify DCE and ICE (resp. Data and Instruction Cache Enable)
> bits in PS (Processor Status) of the system register file.
>
> The core MMU is not used by barebox, however there is a default mapping of
> the memory when the MMU is disabled where only the SMEM and DDR memory are
> cached and device-memory isn't.
>
> Fixes b792124a7d ("rework remap_range")
>
> Signed-off-by: Jules Maselbas <jmaselbas@xxxxxxxxx>
> ---
> arch/kvx/include/asm/mmu.h | 8 ++++++++
> 1 file changed, 8 insertions(+)
> create mode 100644 arch/kvx/include/asm/mmu.h
Applied, thanks
Sascha
>
> diff --git a/arch/kvx/include/asm/mmu.h b/arch/kvx/include/asm/mmu.h
> new file mode 100644
> index 0000000000..d39889bd3f
> --- /dev/null
> +++ b/arch/kvx/include/asm/mmu.h
> @@ -0,0 +1,8 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __ASM_MMU_H
> +#define __ASM_MMU_H
> +
> +#define MAP_ARCH_DEFAULT MAP_CACHED
> +
> +#endif /* __ASM_MMU_H */
> --
> 2.17.1
>
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>
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