Hello Ahmad,
Just for simple simulations we make the ROM size 192MB so it can include all needed artifacts.
When we get this simple system to work we will move the relevant parts to BL2.
DRAM is also simulated now as SRAM so we are not worried about initializations.
So if I understand correctly, we can decide that address 0x10000000 will be reserved for "flash" and add the following node:
flash@0 {
compatible = "mtd-rom";
probe-type = "map_rom";
reg = <0x10000000 0x10000000>;
bank-width = <4>;
device-width = <1>;
#address-cells = <1>;
#size-cells = <1>;
kernel@0 {
label = "kernel";
reg = <0x0 0x01000000>;
};
rootfs@1000000 {
label = "rootfs";
reg = <0x01000000 0x00800000>;
};
};
When I use this node on our DT I see the following devinfo:
barebox:/ devinfo
`-- global
`-- nv
`-- platform
`-- machine
`-- psci.of
`-- 1000000010000000.flash@xxxx
`-- soc.of
`-- c000000000.sram@xxxxxxxxxxxxx
`-- soc:pmu.of
`-- soc:timer.of
`-- e000000000.interrupt-controller@xxxxxxxxxxxxx
`-- mem0
`-- 0x00000000-0x0fffffff ( 256 MiB): /dev/ram0
`-- mem1
`-- 0x00000000-0xffffffffffffffff ( 0 Bytes): /dev/mem
`-- amba
`-- d000307000.serial@xxxxxxxxxxxxx
`-- cs0
`-- 0x00000000-0xffffffffffffffff ( 0 Bytes): /dev/cs0
`-- spi
`-- fs
`-- ramfs0
`-- devfs0
`-- pstore0
Not sure how to proceed from here...
Cheers,
Lior.
> -----Original Message-----
> From: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
> Sent: Monday, June 12, 2023 3:29 PM
> To: Lior Weintraub <liorw@xxxxxxxxxx>; Ahmad Fatoum <ahmad@xxxxxx>;
> barebox@xxxxxxxxxxxxxxxxxxx
> Subject: Re: [PATCH v2] Porting barebox to a new SoC
>
> CAUTION: External Sender
>
> Hello Lior,
>
> On 12.06.23 11:27, Lior Weintraub wrote:
> > Hi Ahmad,
> >
> > Regarding the rootfs and Linux run question:
> > Our board doesn't include eMMC\SD card.
> > We only have our NOR Flash to store the binaries and our BL1 code will make
> sure to copy those blobs into DRAM.
>
> How could BL1 copy artifacts in DRAM when BL2 first needs to set up DRAM?
>
> > The use of QEMU needs to be as simple as possible so no hidden virtio
> drivers and such because we would like to simulate the real HW flow.
>
> cfi-flash is just memory-mapped flash, which is the next simplest thing
> after BL1 copies stuff into (limited-to-4M) on-chip SRAM.
>
> > Our DTS file now includes the GIC, timer and arm,psci-1.0.
> > We have an initial build of Linux kernel Image (using buildroot) and a
> rootfs.cpio.xz.
> > I assume we can somehow reserve a portion of the DRAM to store those
> binaries and let barebox boot this Linux.
>
> You can make this work, but this is not how your actual system will
> look like and trying to make this work is harder than it needs to be.
>
> Just add a cfi-flash that corresponds to the Linux/rootfs flash in
> your actual system, then boot with bootm (type help bootm for info
> on how to use it). You don't need to hardcode the load addresses,
> barebox will determine them automatically.
>
> > Can you please advise how to make it work?
>
> For completion's sake, if you have 64M of RAM that's preloaded with
> boot images:
>
> - Remove the 64M from the barebox /memory node. You can use a different
> DT for kernel, but if you have memory that barebox shouldn't override,
> you need to tell it that.
>
> - Add a mtd-rom node that describes these 64M that you have. You can
> add partitions for the region used for kernel and oftree
>
> - boot with bootm -o /dev/mtdrom0.oftree -r /dev/mtdrom0.initrd \
> /dev/mtdrom0.kernel
>
> That's admittedly cumbersome, but necessary, so barebox knows what
> memory
> it may use for itself and what memory may be used for boot.
>
> Correct solution is to use cfi-flash or similar.
>
> Cheers,
> Ahmad
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