Provide sun50i_mmc0_start_image helper that can be called from PBL to
to easily initialize mmc0 controller and chainload a barebox.bin file
from the first FAT partition.
Signed-off-by: Jules Maselbas <jmaselbas@xxxxxxxx>
---
arch/arm/mach-sunxi/Makefile | 1 +
arch/arm/mach-sunxi/xload-mmc.c | 67 +++++++++++++++++++++++++++++++++
include/mach/sunxi/xload.h | 2 +
3 files changed, 70 insertions(+)
create mode 100644 arch/arm/mach-sunxi/xload-mmc.c
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 0808a21605..fd38462477 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -2,3 +2,4 @@ obj-y += sunxi.o
lwl-y += cpu_init.o
lwl-y += sun50i-a64-ddr3-init.o
lwl-y += sun50i-a64-lpddr3-init.o
+pbl-y += xload-mmc.o
diff --git a/arch/arm/mach-sunxi/xload-mmc.c b/arch/arm/mach-sunxi/xload-mmc.c
new file mode 100644
index 0000000000..9b2d81148e
--- /dev/null
+++ b/arch/arm/mach-sunxi/xload-mmc.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/cache.h>
+#include <linux/bitops.h>
+#include <mach/sunxi/sun50i-regs.h>
+#include <mach/sunxi/sunxi-pinctrl.h>
+#include <mach/sunxi/xload.h>
+
+static void sun50i_mmc0_init(void)
+{
+ void __iomem *ccu = SUN50I_CCU_BASE_ADDR;
+ void __iomem *pio = SUN50I_PIO_BASE_ADDR;
+
+ /* - clock un-gate pinctrl controller */
+ setbits_le32(ccu + CCU_BUS_CLK_GATE2, BIT(5));
+ /* - set mmc alt-function (2) for pins PF5 to PF0 */
+ sunxi_pinmux_set_func(pio, PIO_PF_CFG0, GENMASK(5, 0), 2);
+
+ /* - clock un-gate mmc controller and release reset */
+ setbits_le32(ccu + 0x2c0, /* RST_BUS_MMC0 */ BIT(8));
+ setbits_le32(ccu + 0x060, /* CLK_BUS_MMC0 */ BIT(8));
+ writel(BIT(31), ccu + 0x88); /* MMC0 clock gate */
+}
+
+#if 0 /* currently unused */
+static void sun50i_mmc2_init(void)
+{
+ void __iomem *ccu = SUN50I_CCU_BASE_ADDR;
+ void __iomem *pio = SUN50I_PIO_BASE_ADDR;
+
+ /* - clock un-gate pinctrl controller */
+ setbits_le32(ccu + CCU_BUS_CLK_GATE2, BIT(5));
+ /* - set mmc alt-function (3) for pins PC16 to PC5 */
+ sunxi_pinmux_set_func(pio, PIO_PC_BASE, GENMASK(16, 5), 3);
+
+ /* - clock un-gate mmc controller and release reset */
+ setbits_le32(ccu + 0x2c0, /* RST_BUS_MMC2 */ BIT(10));
+ setbits_le32(ccu + 0x060, /* CLK_BUS_MMC2 */ BIT(10));
+ writel(BIT(31), ccu + 0x90); /* MMC2 clock gate */
+}
+#endif
+
+static void sunxi_fat_start_image(struct pbl_bio *bio, void *buf, size_t size)
+{
+ void (*start)(void) = buf;
+ int ret;
+
+ ret = pbl_fat_load(bio, "barebox.bin", buf, size);
+ if (ret < 0)
+ return;
+ sync_caches_for_execution();
+ start();
+}
+
+void sun50i_mmc0_start_image(void)
+{
+ struct pbl_bio bio;
+ int ret;
+
+ sun50i_mmc0_init();
+
+ ret = sunxi_mmc_bio_init(&bio, SUN50I_MMC0_BASE_ADDR, 24000000, 0);
+ if (ret)
+ return;
+ sunxi_fat_start_image(&bio, IOMEM(SUN50I_DRAM_ADDR), SZ_16M);
+}
diff --git a/include/mach/sunxi/xload.h b/include/mach/sunxi/xload.h
index f978db4951..005f78b5c5 100644
--- a/include/mach/sunxi/xload.h
+++ b/include/mach/sunxi/xload.h
@@ -9,4 +9,6 @@
int sunxi_mmc_bio_init(struct pbl_bio *bio, void __iomem *base,
unsigned int clock, unsigned int slot);
+void sun50i_mmc0_start_image(void);
+
#endif
--
2.40.1
