On 19.05.23 12:09, Jules Maselbas wrote: > On Thu, May 18, 2023 at 08:46:56PM +0200, Ahmad Fatoum wrote: >> On 11.05.23 01:37, Jules Maselbas wrote: >>> +menuconfig SUNXI_MULTI_BOARDS >>> + bool "Allwinner boards" >>> + select HAVE_PBL_MULTI_IMAGES >>> + select RELOCATABLE >> >> Just make this the default? > by putting this into ARCH_SUNXI ? Just drop the SUNXI_MULTI_BOARDS and select HAVE_PBL_MULTI_IMAGES and RELOCATABLE directly from ARCH_SUNXI. >>> + /* UART0 clock enable */ >>> + setbits_le32(ccu + CCU_BUS_CLK_GATE3, 1u << 16); >>> + /* UART0 release reset */ >>> + setbits_le32(ccu + CCU_BUS_SOFT_RST4, 1u << 16); >> >> Can the pads UART0 uses be muxed otherwise? Is it ok to unconditionally > To be clear: nothing touches the pin-muxes here, only clock-gate and reset > for gpio and uart. UART0 isn't muxed by default, it can be either muxed to > PB8/PB9 or PF2/PF4. To enable UART0 on PB8/PB9 you will to write 0x-----33- > into PIO PB_CFG1(0x28) register. Which I didn't do here... I think that's > because the boot ROM has done it... or i am missing something. I see. Still it's odd that UART0 specific stuff is done in lowlevel init. >>> diff --git a/include/mach/sunxi/sunxi-pinctrl.h b/include/mach/sunxi/sunxi-pinctrl.h >>> new file mode 100644 >>> index 0000000000..adb2a24577 >>> --- /dev/null >>> +++ b/include/mach/sunxi/sunxi-pinctrl.h >>> @@ -0,0 +1,13 @@ >>> +/* pio aka "allwinner,sun8i-h3-pinctrl" */ >> >> No include guard? > ... this file could be merged in "sun50i-regs.h", what do you think ? Either is fine by me. Cheers, Ahmad -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
