On 17.05.23 11:03, Sascha Hauer wrote:
> pmd_flags_to_pte() assumed ARMv7 page table format. This has the effect
> that random bit values end up in the access permission bits. This works
^ for older CPUs.
> because the domain is configured as manager in the DACR and thus the
^ for non-ARMv7
> access permissions are ignored by the MMU.
> Nevertheless fix this and take the cpu architecture into account when
> translating the bits. Don't bother to translate the access permission
> bits though, just hardcode them as PTE_SMALL_AP_UNO_SRW.
>
> Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
Apart from that:
Acked-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
> ---
> arch/arm/cpu/mmu_32.c | 27 ++++++++++++++++-----------
> 1 file changed, 16 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/cpu/mmu_32.c b/arch/arm/cpu/mmu_32.c
> index 7cd732580e..4abaab7d87 100644
> --- a/arch/arm/cpu/mmu_32.c
> +++ b/arch/arm/cpu/mmu_32.c
> @@ -167,17 +167,22 @@ static u32 pmd_flags_to_pte(u32 pmd)
> pte |= PTE_BUFFERABLE;
> if (pmd & PMD_SECT_CACHEABLE)
> pte |= PTE_CACHEABLE;
> - if (pmd & PMD_SECT_nG)
> - pte |= PTE_EXT_NG;
> - if (pmd & PMD_SECT_XN)
> - pte |= PTE_EXT_XN;
> -
> - /* TEX[2:0] */
> - pte |= PTE_EXT_TEX((pmd >> 12) & 7);
> - /* AP[1:0] */
> - pte |= ((pmd >> 10) & 0x3) << 4;
> - /* AP[2] */
> - pte |= ((pmd >> 15) & 0x1) << 9;
> +
> + if (cpu_architecture() >= CPU_ARCH_ARMv7) {
> + if (pmd & PMD_SECT_nG)
> + pte |= PTE_EXT_NG;
> + if (pmd & PMD_SECT_XN)
> + pte |= PTE_EXT_XN;
> +
> + /* TEX[2:0] */
> + pte |= PTE_EXT_TEX((pmd >> 12) & 7);
> + /* AP[1:0] */
> + pte |= ((pmd >> 10) & 0x3) << 4;
> + /* AP[2] */
> + pte |= ((pmd >> 15) & 0x1) << 9;
> + } else {
> + pte |= PTE_SMALL_AP_UNO_SRW;
> + }
>
> return pte;
> }
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