On 17.05.23 11:03, Sascha Hauer wrote:
> This is a preparation for using two level page tables in the PBL.
> To do that we need a way to allocate page tables in PBL. As malloc
> is not available in PBL, increase the area we use for the TTB to
> make some space available for page tables.
>
> Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
Reviewed-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
> ---
> arch/arm/cpu/mmu_32.c | 6 ++++++
> arch/arm/include/asm/barebox-arm.h | 8 ++------
> 2 files changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/cpu/mmu_32.c b/arch/arm/cpu/mmu_32.c
> index 12fe892400..4050d96846 100644
> --- a/arch/arm/cpu/mmu_32.c
> +++ b/arch/arm/cpu/mmu_32.c
> @@ -24,6 +24,12 @@
> #define PTRS_PER_PTE (PGDIR_SIZE / PAGE_SIZE)
> #define ARCH_MAP_WRITECOMBINE ((unsigned)-1)
>
> +/*
> + * We have a 4GiB address space split into 1MiB sections, with each
> + * section header taking 4 bytes
> + */
> +#define ARM_TTB_SIZE (SZ_4G / SZ_1M * sizeof(u32))
> +
> static uint32_t *ttb;
>
> /*
> diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
> index f5a74b4746..eb31ca2788 100644
> --- a/arch/arm/include/asm/barebox-arm.h
> +++ b/arch/arm/include/asm/barebox-arm.h
> @@ -23,11 +23,7 @@
> #include <asm/reloc.h>
> #include <linux/stringify.h>
>
> -/*
> - * We have a 4GiB address space split into 1MiB sections, with each
> - * section header taking 4 bytes
> - */
> -#define ARM_TTB_SIZE (SZ_4G / SZ_1M * sizeof(u32))
> +#define ARM_EARLY_PAGETABLE_SIZE SZ_64K
>
> void __noreturn barebox_arm_entry(unsigned long membase, unsigned long memsize, void *boarddata);
>
> @@ -89,7 +85,7 @@ static inline unsigned long arm_mem_stack(unsigned long endmem)
> static inline unsigned long arm_mem_ttb(unsigned long endmem)
> {
> endmem = arm_mem_stack(endmem);
> - endmem = ALIGN_DOWN(endmem, ARM_TTB_SIZE) - ARM_TTB_SIZE;
> + endmem = ALIGN_DOWN(endmem, ARM_EARLY_PAGETABLE_SIZE) - ARM_EARLY_PAGETABLE_SIZE;
>
> return endmem;
> }
--
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