We have upstream device trees in dts/src/arm64/rockchip/rk3588*.dtsi.
This patch adds some pieces not yet in upstream, like PCIe nodes,
DMC node and sdmmc node.
Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
---
arch/arm/dts/rk3588.dtsi | 152 ++++++++++++++++++++++++++++++++++++++
arch/arm/dts/rk3588s.dtsi | 135 +++++++++++++++++++++++++++++++++
2 files changed, 287 insertions(+)
create mode 100644 arch/arm/dts/rk3588.dtsi
create mode 100644 arch/arm/dts/rk3588s.dtsi
diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi
new file mode 100644
index 0000000000..28bcb2f643
--- /dev/null
+++ b/arch/arm/dts/rk3588.dtsi
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/phy/phy.h>
+#include "rk3588s.dtsi"
+
+/ {
+ pcie30_phy_grf: syscon@fd5b8000 {
+ compatible = "rockchip,pcie30-phy-grf", "syscon";
+ reg = <0x0 0xfd5b8000 0x0 0x10000>;
+ };
+
+ pipe_phy0_grf: syscon@fd5bc000 {
+ compatible = "rockchip,pipe-phy-grf", "syscon";
+ reg = <0x0 0xfd5bc000 0x0 0x100>;
+ };
+
+ pipe_phy1_grf: syscon@fd5c0000 {
+ compatible = "rockchip,pipe-phy-grf", "syscon";
+ reg = <0x0 0xfd5c0000 0x0 0x100>;
+ };
+
+ pcie3x4: pcie@fe150000 {
+ compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0x0f>;
+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ num-ib-windows = <16>;
+ num-ob-windows = <16>;
+ num-viewport = <8>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3588_PD_PCIE>;
+ ranges = <0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000
+ 0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0xe00000
+ 0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
+ reg = <0x0 0xfe150000 0x0 0x10000>,
+ <0xa 0x40000000 0x0 0x400000>,
+ <0x0 0xf0000000 0x0 0x100000>;
+ reg-names = "apb", "dbi", "config";
+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+ reset-names = "pcie", "periph";
+ rockchip,pipe-grf = <&php_grf>;
+ status = "disabled";
+ };
+
+ pcie3x2: pcie@fe160000 {
+ compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x10 0x1f>;
+ clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
+ <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
+ <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ num-ib-windows = <16>;
+ num-ob-windows = <16>;
+ num-viewport = <8>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3588_PD_PCIE>;
+ ranges = <0x81000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x100000
+ 0x82000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0xe00000
+ 0xc3000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>;
+ reg = <0x0 0xfe160000 0x0 0x10000>,
+ <0xa 0x40400000 0x0 0x400000>,
+ <0x0 0xf1000000 0x0 0x100000>;
+ reg-names = "apb", "dbi", "config";
+ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
+ reset-names = "pcie", "periph";
+ rockchip,pipe-grf = <&php_grf>;
+ status = "disabled";
+ };
+
+ pcie2x1l0: pcie@fe170000 {
+ compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x20 0x2f>;
+ clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
+ <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
+ <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ device_type = "pci";
+ linux,pci-domain = <2>;
+ num-ib-windows = <8>;
+ num-ob-windows = <8>;
+ num-viewport = <4>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ phys = <&combphy1_ps PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ ranges = <0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000
+ 0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0xe00000
+ 0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
+ reg = <0x0 0xfe170000 0x0 0x10000>,
+ <0xa 0x40800000 0x0 0x400000>,
+ <0x0 0xf2000000 0x0 0x100000>;
+ reg-names = "apb", "dbi", "config";
+ resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
+ reset-names = "pcie", "periph";
+ rockchip,pipe-grf = <&php_grf>;
+ status = "disabled";
+ };
+
+ combphy1_ps: phy@fee10000 {
+ compatible = "rockchip,rk3588-naneng-combphy";
+ reg = <0x0 0xfee10000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
+ <&cru PCLK_PHP_ROOT>;
+ clock-names = "refclk", "apbclk", "phpclk";
+ assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_P_PCIE2_PHY1>, <&cru SRST_REF_PIPE_PHY1>;
+ reset-names = "combphy-apb", "combphy";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
+ rockchip,pcie1ln-sel-bits = <0x100 0 0 0>;
+ status = "disabled";
+ };
+
+ pcie30phy: phy@fee80000 {
+ compatible = "rockchip,rk3588-pcie3-phy";
+ reg = <0x0 0xfee80000 0x0 0x20000>;
+ #phy-cells = <0>;
+ clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
+ clock-names = "pclk";
+ resets = <&cru SRST_PCIE30_PHY>;
+ reset-names = "phy";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,phy-grf = <&pcie30_phy_grf>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi
new file mode 100644
index 0000000000..ba6561f97e
--- /dev/null
+++ b/arch/arm/dts/rk3588s.dtsi
@@ -0,0 +1,135 @@
+/ {
+ dmc: memory-controller {
+ compatible = "rockchip,rk3588-dmc";
+ rockchip,pmu = <&pmugrf>;
+ };
+
+ pmugrf: syscon@fd58a000 {
+ compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
+ reg = <0x0 0xfd58a000 0x0 0x10000>;
+ };
+
+ pipe_phy2_grf: syscon@fd5c4000 {
+ compatible = "rockchip,pipe-phy-grf", "syscon";
+ reg = <0x0 0xfd5c4000 0x0 0x100>;
+ };
+
+ pcie2x1l1: pcie@fe180000 {
+ compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x30 0x3f>;
+ clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
+ <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
+ <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ device_type = "pci";
+ linux,pci-domain = <3>;
+ num-ib-windows = <8>;
+ num-ob-windows = <8>;
+ num-viewport = <4>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ phys = <&combphy2_psu PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ ranges = <0x81000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x100000
+ 0x82000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0xe00000
+ 0xc3000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;
+ reg = <0x0 0xfe180000 0x0 0x10000>,
+ <0xa 0x40c00000 0x0 0x400000>,
+ <0x0 0xf3000000 0x0 0x100000>;
+ reg-names = "apb", "dbi", "config";
+ resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
+ reset-names = "pcie", "periph";
+ rockchip,pipe-grf = <&php_grf>;
+ status = "disabled";
+ };
+
+ pcie2x1l2: pcie@fe190000 {
+ compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x40 0x4f>;
+ clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
+ <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
+ <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ device_type = "pci";
+ linux,pci-domain = <4>;
+ num-ib-windows = <8>;
+ num-ob-windows = <8>;
+ num-viewport = <4>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ phys = <&combphy0_ps PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ ranges = <0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000
+ 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe00000
+ 0xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
+ reg = <0x0 0xfe190000 0x0 0x10000>,
+ <0xa 0x41000000 0x0 0x400000>,
+ <0x0 0xf4000000 0x0 0x100000>;
+ reg-names = "apb", "dbi", "config";
+ resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
+ reset-names = "pcie", "periph";
+ rockchip,pipe-grf = <&php_grf>;
+ status = "disabled";
+ };
+
+ sdmmc: mmc@fe2c0000 {
+ compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xfe2c0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
+ power-domains = <&power RK3588_PD_SDMMC>;
+ status = "disabled";
+ };
+
+ combphy0_ps: phy@fee00000 {
+ compatible = "rockchip,rk3588-naneng-combphy";
+ reg = <0x0 0xfee00000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
+ <&cru PCLK_PHP_ROOT>;
+ clock-names = "refclk", "apbclk", "phpclk";
+ assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;
+ reset-names = "combphy-apb", "combphy";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
+ status = "disabled";
+ };
+
+ combphy2_psu: phy@fee20000 {
+ compatible = "rockchip,rk3588-naneng-combphy";
+ reg = <0x0 0xfee20000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
+ <&cru PCLK_PHP_ROOT>;
+ clock-names = "refclk", "apbclk", "phpclk";
+ assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_P_PCIE2_PHY2>, <&cru SRST_REF_PIPE_PHY2>;
+ reset-names = "combphy-apb", "combphy";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
+ rockchip,pcie1ln-sel-bits = <0x100 1 1 0>;
+ status = "disabled";
+ };
+};
+
+&scmi_clk {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
+};
--
2.39.2
