On Sun, Mar 12, 2023 at 05:29:28PM +0100, Marco Felsch wrote:
> since commit f083fffe52 ("ARM: dts: i.MX8MP: add DDRC compatibles") we
> make use of the esdctl driver. This cause the below error since barebox
> try to add the memory twice.
>
> | imx-esdctl 3d400000.memory-controller@xxxxxxxxxxx: probe failed: Device or resource busy
> | initcall imx_esdctl_driver_init+0x0/0x2c failed: No such device
>
> Remove the memory node to fix this.
>
> This behaviour was seen on a i.mx8mp-evk but the
> imx8mp-tqma8mpql-mba8mpxl also has a memory node and includes the
> barebox.dtsi.
>
> Fixes: f083fffe52 ("ARM: dts: i.MX8MP: add DDRC compatibles")
> Signed-off-by: Marco Felsch <m.felsch@xxxxxxxxxxxxxx>
> ---
> arch/arm/dts/imx8mp-evk.dts | 2 ++
> arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts | 2 ++
> 2 files changed, 4 insertions(+)
Applied for now as it fixes a regression.
For the longer run I'd like to try another approach:
On i.MX as well as on other SoCs we read the DDR resources from the
memory controller. When we do this it should take precedence over the
device tree memory nodes. If reading from the memory controller returns
wrong DDR resources then this is a bug that should be fixed. Trying to
merge the memory banks read from the controller with the ones from the
device tree likely doesn't improve the situation.
Therefore the memory controller should register the memory banks along
with some we-know-it-better flag which disables reading the memory
nodes from the device tree. This leaves reading the memory nodes from
the device tree for the cases where no memory controller driver is
available.
There are some known cases where the memory controller is configured
with bigger SDRAM than is actually equipped on the board. We'll find
the memory mirrored than in the registered memory banks. For i.MX
we have imx_esdctl_disable() for this case, the same could be done
for other SoCs as well if needed.
Sascha
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