On Thu, Feb 16, 2023 at 11:54:14AM +0000, Renaud Barbier wrote:
>
>
> > > +
> > > +/* Currently 1000FD is not working. Below is a bit of guess work
> > > + * from reading MMD3/MMD7 of the AR8033 */ static int
> > > +phy_fixup(struct phy_device *phydev) {
> > > + unsigned short val;
> > > + int advertise = SUPPORTED_1000baseT_Full |
> > > +SUPPORTED_1000baseT_Half;
> > > +
> > > + phydev->advertising &= ~advertise;
> > > +
> > > + /* Ar8031 phy SmartEEE feature cause link status generates glitch,
> > > + * which cause ethernet link down/up issue, so disable SmartEEE
> > > + */
> > > + phy_write(phydev, 0xd, 0x3);
> > > + phy_write(phydev, 0xe, 0x805d);
> > > + phy_write(phydev, 0xd, 0x4003);
> > > + val = phy_read(phydev, 0xe);
> > > + val &= ~(0x1 << 8);
> > > + phy_write(phydev, 0xe, val);
> > > +
> > > + /* Use XTAL */
> > > + phy_write(phydev, 0xd, 0x7);
> > > + phy_write(phydev, 0xe, 0x8016);
> > > + phy_write(phydev, 0xd, 0x4007);
> > > + val = phy_read(phydev, 0xe);
> > > + val &= 0xffe3;
> > > + phy_write(phydev, 0xe, val);
> > > +
> > > + return 0;
> > > +}
> >
> > We have a phy driver for the AR8033. Can you use it instead of putting this
> > into board code?
>
> Hello I have enabled the at803x driver to support the AR8031. However, only the generic PHY driver config_init get called.
> phy_driver_register: 00000000
> register generic for: Generic PHY, 0xffffffff
> phy_driver_register: bbe15d54
> register specific for: Atheros 8035 ethernet, 0x4dd072
> phy_driver_register: bbe15d54
> register specific for: Atheros 8030 ethernet, 0x4dd076
> phy_driver_register: bbe15d54
> register specific for: Atheros 8031 ethernet, 0x4dd074
>
> call phy_init_hw
> call config_init for: Generic PHY, 0xffffffff
>
> I do not understand how to connect the AR802x phy driver to the device. Do I need to add something to the device tree?
>
> barebox@LS1021A-IOT Board:/ md -w -s /dev/mdio0-phy03
Is this the only phy or are there others? What does "devinfo mdio0-phy03" say?
miitool -v output might be interesting as well.
I had a short look at your changes to the gianfar driver. You added
this:
+ priv->phyaddr = -1;
+ np = of_parse_phandle_from(dev->device_node, NULL, "phy-handle", 0);
+ if (np) {
+ struct device_node *parent;
+ uint32_t reg = 0;
+
+ /* Get mdio parent */
+ parent = of_get_parent(np);
+ if (!parent) {
+ pr_err("No parent node for phy-handle\n");
+ return PTR_ERR(parent);
+ }
+ priv->gfar_mdio = parent->dev->priv;
+ if (!of_property_read_u32(np, "reg", ®))
+ priv->phyaddr = reg;
+ }
This is not necessary when your phy is described in the device tree. You
neither need the mdiobus in the ethernet driver nor the phy address.
Instead, just call:
ret = phy_device_connect(edev, NULL, -1, gfar_adjust_link, 0, interface);
phy_device_connect() will parse the phy-handle property then and connect
the ethernet device to the correct phy.
I am not sure though if that's part of your problem, because correctly
open coding what phy_device_connect() does should have the same effect.
Sascha
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