DMA allocations should be aligned on a cache line size, at least on
cache non-coherent MIPS systems. Instead of using some hardcoded value
for an alignment from a generic implementation (which may be wrong for
us), we can get cache info from 'current_cpu_data' variable, so use it.
Signed-off-by: Denis Orlov <denorl2009@xxxxxxxxx>
---
arch/mips/include/asm/dma.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h
index e0b4689172..49eeaac1a2 100644
--- a/arch/mips/include/asm/dma.h
+++ b/arch/mips/include/asm/dma.h
@@ -6,6 +6,18 @@
#ifndef __ASM_DMA_H
#define __ASM_DMA_H
+#include <common.h>
+#include <xfuncs.h>
+#include <asm/cpu-info.h>
+
+#define dma_alloc dma_alloc
+static inline void *dma_alloc(size_t size)
+{
+ unsigned long max_linesz = max(current_cpu_data.dcache.linesz,
+ current_cpu_data.scache.linesz);
+ return xmemalign(max_linesz, ALIGN(size, max_linesz));
+}
+
#include "asm/dma-mapping.h"
#endif /* __ASM_DMA_H */
--
2.30.2
