Hi Lucas,
On 23-02-06, Lucas Stach wrote:
> All i.MX8M* DDRC nodes are compatible to "fsl,imx8m-ddrc". As the memory
> size detection works the same on all of them, there is no need to match
> the more specific compatible.
>
> Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> ---
> arch/arm/mach-imx/esdctl.c | 8 +-------
> 1 file changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
> index 043de477a77d..2a2bc5205301 100644
> --- a/arch/arm/mach-imx/esdctl.c
> +++ b/arch/arm/mach-imx/esdctl.c
> @@ -732,13 +732,7 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = {
> .compatible = "fsl,vf610-ddrmc",
> .data = &vf610_data
> }, {
> - .compatible = "fsl,imx8mm-ddrc",
> - .data = &imx8mq_data
> - }, {
> - .compatible = "fsl,imx8mn-ddrc",
> - .data = &imx8mn_data
The i.MX8M Nano uses a 16bit bus width according the data. I don't have
the datasheet right now to check this. But this commit will change it to
32 bit, is this allowed?
Regards,
Marco
> - }, {
> - .compatible = "fsl,imx8mq-ddrc",
> + .compatible = "fsl,imx8m-ddrc",
> .data = &imx8mq_data
> }, {
> .compatible = "fsl,imx7d-ddrc",
> --
> 2.39.1
>
>
>
