The i.MX6 includes some on-chip RAM: 128KiB on most variants, with 256KiB on the Dual and Quad variants. This region is where the first stage of Barebox gets loaded if RAM initialization isn't hard coded using DCD information. Add the base address and size so it can be used to calculate where to put the stack at boot. Signed-off-by: John Watts <contact@xxxxxxxxxx> --- arch/arm/mach-imx/include/mach/imx6-regs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h index 39e2751533..4acbb9796b 100644 --- a/arch/arm/mach-imx/include/mach/imx6-regs.h +++ b/arch/arm/mach-imx/include/mach/imx6-regs.h @@ -3,6 +3,10 @@ #ifndef __MACH_IMX6_REGS_H #define __MACH_IMX6_REGS_H +/* Set MAX_SIZE to 128K, only the Quad and Dual have 256K */ +#define MX6_OCRAM_BASE_ADDR 0x00900000 +#define MX6_OCRAM_MAX_SIZE 0x00100000 + #define MX6_APBH_BASE_ADDR 0x00110000 #define MX6_GPMI_BASE_ADDR 0x00112000 #define MX6_BCH_BASE_ADDR 0x00114000 -- 2.39.1
