On 23.01.23 21:18, John Watts wrote:
> The MPWLGCR registers clear the error bits before software can read them,
> so rely on the MPWLHWERR registers for error reporting instead.
>
> This errata was announced in 2019 and seems to apply to all chip revisions.
>
> U-Boot contains a different workaround where it checks the calibration data
> for the result 0x001F001F (maximum delay) and flag that as a failure.
> This workaround seems to first publicly appear in the Novena U-Boot code
> and originate from Freescale internal code or documentation.
>
> While we're at it, fix the comment implying this code only checks PHY0 in x32
> configuration. This is wrong and misleading.
>
> Signed-off-by: John Watts <contact@xxxxxxxxxx>
> ---
> arch/arm/mach-imx/imx6-mmdc.c | 18 ++++++++++++++----
> arch/arm/mach-imx/include/mach/imx6-mmdc.h | 1 +
> 2 files changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c
> index 00b8d30d69..908771626a 100644
> --- a/arch/arm/mach-imx/imx6-mmdc.c
> +++ b/arch/arm/mach-imx/imx6-mmdc.c
> @@ -11,6 +11,18 @@
> #include <mach/imx6-regs.h>
> #include <mach/imx6.h>
>
> +static bool wlcalib_failed(void __iomem *ips)
> +{
> + int i;
> +
> + for (i = 0; i < 4; ++i) {
> + if (readb(P0_IPS + MPWLHWERR + i) == 0)
s/P0_OPS/ips/ ?
Also does it need to be bytewise reads? If not, you could rewrite
as return readl(ips + MPWLHWERR) == 0;
> + return true;
Write level calibration has failed when MPWLHWERR == 0 and succeeded
when there is some other value? That sounds odd.
> + }
> +
> + return false;
> +}
> +
> int mmdc_do_write_level_calibration(void)
> {
> u32 esdmisc_val, zq_val;
> @@ -56,11 +68,9 @@ int mmdc_do_write_level_calibration(void)
> /* Upon completion of this process the MMDC de-asserts the MPWLGCR[HW_WL_EN] */
> while (readl(P0_IPS + MPWLGCR) & 0x00000001);
>
> - /* check for any errors: check both PHYs for x64 configuration, if x32, check only PHY0 */
> - if ((readl(P0_IPS + MPWLGCR) & 0x00000F00) ||
> - (readl(P1_IPS + MPWLGCR) & 0x00000F00)) {
> + /* check for any errors on both PHYs */
> + if (wlcalib_failed(P0_IPS) || wlcalib_failed(P1_IPS))
> errorcount++;
> - }
>
> pr_debug("Write leveling calibration completed\n");
>
> diff --git a/arch/arm/mach-imx/include/mach/imx6-mmdc.h b/arch/arm/mach-imx/include/mach/imx6-mmdc.h
> index bda20aba17..098ba4f5bf 100644
> --- a/arch/arm/mach-imx/include/mach/imx6-mmdc.h
> +++ b/arch/arm/mach-imx/include/mach/imx6-mmdc.h
> @@ -18,6 +18,7 @@
> #define MPWLGCR 0x808
> #define MPWLDECTRL0 0x80c
> #define MPWLDECTRL1 0x810
> +#define MPWLHWERR 0x878
> #define MPPDCMPR1 0x88c
> #define MPSWDAR 0x894
> #define MPRDDLCTL 0x848
--
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