[PATCH 7/7] ARM: i.MX8M: init CAAM when CONFIG_FSL_CAAM_RNG_PBL_INIT

[Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>]

Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
---
 arch/arm/mach-imx/Kconfig                   |  1 +
 arch/arm/mach-imx/atf.c                     | 10 ++++++++++
 arch/arm/mach-imx/include/mach/imx8m-regs.h |  3 +++
 drivers/crypto/caam/Kconfig                 |  3 ++-
 4 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 84b763f83fb1..774c4cacb7f7 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -184,6 +184,7 @@ config ARCH_IMX8M
 	select IMX8M_DRAM
 	select PBL_VERIFY_PIGGY if HABV4
 	select ARM_USE_COMPRESSED_DTB
+	imply FSL_CAAM_RNG_PBL_INIT if HAVE_OPTEE
 
 config ARCH_IMX8MM
 	select ARCH_IMX8M
diff --git a/arch/arm/mach-imx/atf.c b/arch/arm/mach-imx/atf.c
index 61b602816623..2a3e3f53b885 100644
--- a/arch/arm/mach-imx/atf.c
+++ b/arch/arm/mach-imx/atf.c
@@ -8,6 +8,7 @@
 #include <mach/xload.h>
 #include <mach/romapi.h>
 #include <soc/fsl/fsl_udc.h>
+#include <soc/fsl/caam.h>
 
 /**
  * imx8m_atf_load_bl31 - Load ATF BL31 blob and transfer control to it
@@ -38,9 +39,18 @@
 static __noreturn void imx8m_atf_start_bl31(const void *fw, size_t fw_size, void *atf_dest)
 {
 	void __noreturn (*bl31)(void) = atf_dest;
+	int ret;
 
 	BUG_ON(fw_size > MX8M_ATF_BL31_SIZE_LIMIT);
 
+	if (IS_ENABLED(CONFIG_FSL_CAAM_RNG_PBL_INIT)) {
+		ret = imx_early_caam_init(MX8M_CAAM_BASE_ADDR);
+		if (ret)
+			pr_debug("CAAM early init failed: %d\n", ret);
+		else
+			pr_debug("CAAM early init successful\n");
+	}
+
 	memcpy(bl31, fw, fw_size);
 
 	asm volatile("msr sp_el2, %0" : :
diff --git a/arch/arm/mach-imx/include/mach/imx8m-regs.h b/arch/arm/mach-imx/include/mach/imx8m-regs.h
index 794e1bdd88a4..d101b88cc4a6 100644
--- a/arch/arm/mach-imx/include/mach/imx8m-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx8m-regs.h
@@ -3,6 +3,8 @@
 #ifndef __MACH_IMX8M_REGS_H
 #define __MACH_IMX8M_REGS_H
 
+#include <linux/compiler.h>
+
 /*
  * Actual addressable OCRAM size may differ from SoC to SoC, but all of
  * i.MX8MQ/M/N/P have this region of MMIO address space set aside for
@@ -31,6 +33,7 @@
 #define MX8M_UART1_BASE_ADDR		0x30860000
 #define MX8M_UART3_BASE_ADDR		0x30880000
 #define MX8M_UART2_BASE_ADDR		0x30890000
+#define MX8M_CAAM_BASE_ADDR		IOMEM(0x30900000)
 #define MX8M_I2C1_BASE_ADDR		0x30A20000
 #define MX8M_I2C2_BASE_ADDR		0x30A30000
 #define MX8M_I2C3_BASE_ADDR		0x30A40000
diff --git a/drivers/crypto/caam/Kconfig b/drivers/crypto/caam/Kconfig
index 33d7b0fb8329..e7f57708f3ea 100644
--- a/drivers/crypto/caam/Kconfig
+++ b/drivers/crypto/caam/Kconfig
@@ -36,4 +36,5 @@ config CRYPTO_DEV_FSL_CAAM_RNG
 	  Selecting this will register the SEC4 hardware rng.
 
 config FSL_CAAM_RNG_PBL_INIT
-	bool
+	bool "Setup CAAM in EL3"
+	depends on ARCH_IMX8M
-- 
2.30.2