On 09.12.22 19:37, Ahmad Fatoum wrote: >> From my debugging I can see that the Layerscape PCIE driver use VA address = PA address = 0x24000000 >> >> So Is the problem I am seeing an issue with mapping the correct physical address for a 32-bit processor? >> >> If yes, how can I map the 64-bit PA to a 32-bit VA? > > Normally, you would call map_io_sections as pci-tegra does, but in your > case this alone is insufficient as you will need to implement ARM32 LPAE > support first. Once that's in place, you can use map_io_sections and map > it to e.g. 0x24000000 as U-Boot does arch/arm/cpu/armv7/ls102xa/cpu.c mmu_setup(). > > U-Boot LPAE support was added to support Rpi2, which starts in HYP mode, but we had > worked around that in barebox to not require LPAE. For your case however, I don't believe > there's a way around using LPAE page tables. > > Tangentially related: I don't know how the PCI controller maintains cache coherency, > but if it does write back through CPU caches, you may observe memory corruption. > > It may be the safest for you to disable cache snooping for PCIe until that's > resolved (We've this planned, but it will probably not happen this year. > If you're interested I can elaborate). I should have shortened the context a bit. Posting again in case you missed it. > > Cheers, > Ahmad > > > >> >> Cheers, >> Renaud >> >> >> >> >> > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
