Hi Sascha,
On 22-11-01, Sascha Hauer wrote:
> We have a set of GPMI register defines in include/, so use them for the
> xload driver as well.
>
> Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> ---
> arch/arm/mach-imx/xload-gpmi-nand.c | 66 ++++++++---------------------
> 1 file changed, 17 insertions(+), 49 deletions(-)
>
> diff --git a/arch/arm/mach-imx/xload-gpmi-nand.c b/arch/arm/mach-imx/xload-gpmi-nand.c
> index 3a4f331ce6..6ac9af762f 100644
> --- a/arch/arm/mach-imx/xload-gpmi-nand.c
> +++ b/arch/arm/mach-imx/xload-gpmi-nand.c
> @@ -11,6 +11,7 @@
> #include <mach/xload.h>
> #include <soc/imx/imx-nand-bcb.h>
> #include <linux/mtd/rawnand.h>
> +#include <soc/imx/gpmi-nand.h>
> #include <mach/imx6-regs.h>
> #include <mach/clock-imx6.h>
missing bitfield.h include.
Also should we say in the commit message that we are using the
FIELD_PREP now by this change?
Regards,
Marco
>
> @@ -203,39 +204,6 @@ static int mxs_dma_run(struct mxs_dma_chan *pchan, struct mxs_dma_cmd *pdesc,
>
> /* ----------------------------- NAND driver part -------------------------- */
>
> -#define GPMI_CTRL0 0x00000000
> -#define GPMI_CTRL0_RUN (1 << 29)
> -#define GPMI_CTRL0_DEV_IRQ_EN (1 << 28)
> -#define GPMI_CTRL0_UDMA (1 << 26)
> -#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24)
> -#define GPMI_CTRL0_COMMAND_MODE_OFFSET 24
> -#define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24)
> -#define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24)
> -#define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24)
> -#define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24)
> -#define GPMI_CTRL0_WORD_LENGTH (1 << 23)
> -#define GPMI_CTRL0_CS(cs) ((cs) << 20)
> -#define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17)
> -#define GPMI_CTRL0_ADDRESS_OFFSET 17
> -#define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17)
> -#define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17)
> -#define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17)
> -#define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16)
> -#define GPMI_CTRL0_XFER_COUNT_MASK 0xffff
> -#define GPMI_CTRL0_XFER_COUNT_OFFSET 0
> -
> -#define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13)
> -#define GPMI_ECCCTRL_ENABLE_ECC (1 << 12)
> -#define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff
> -
> -#define BCH_CTRL 0x00000000
> -#define BCH_CTRL_COMPLETE_IRQ (1 << 0)
> -
> -#define MXS_NAND_DMA_DESCRIPTOR_COUNT 6
> -#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
> -#define MXS_NAND_METADATA_SIZE 10
> -#define MXS_NAND_COMMAND_BUFFER_SIZE 128
> -
> struct mxs_nand_info {
> void __iomem *io_base;
> void __iomem *bch_base;
> @@ -352,7 +320,7 @@ static int mxs_nand_read_page(struct mxs_nand_info *info, int writesize,
>
> d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE |
> GPMI_CTRL0_WORD_LENGTH |
> - GPMI_CTRL0_CS(info->cs) |
> + FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
> GPMI_CTRL0_ADDRESS_NAND_CLE |
> GPMI_CTRL0_ADDRESS_INCREMENT |
> cmd_queue_len;
> @@ -372,7 +340,7 @@ static int mxs_nand_read_page(struct mxs_nand_info *info, int writesize,
>
> d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE |
> GPMI_CTRL0_WORD_LENGTH |
> - GPMI_CTRL0_CS(info->cs) |
> + FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
> GPMI_CTRL0_ADDRESS_NAND_CLE |
> GPMI_CTRL0_ADDRESS_INCREMENT |
> cmd_queue_len;
> @@ -386,7 +354,7 @@ static int mxs_nand_read_page(struct mxs_nand_info *info, int writesize,
>
> d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
> GPMI_CTRL0_WORD_LENGTH |
> - GPMI_CTRL0_CS(info->cs) |
> + FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
> GPMI_CTRL0_ADDRESS_NAND_DATA;
>
> if (raw) {
> @@ -398,7 +366,7 @@ static int mxs_nand_read_page(struct mxs_nand_info *info, int writesize,
> DMACMD_COMMAND_DMA_WRITE;
> d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_READ |
> GPMI_CTRL0_WORD_LENGTH |
> - GPMI_CTRL0_CS(info->cs) |
> + FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
> GPMI_CTRL0_ADDRESS_NAND_DATA |
> (writesize + oobsize);
> d->address = (dma_addr_t)databuf;
> @@ -408,7 +376,7 @@ static int mxs_nand_read_page(struct mxs_nand_info *info, int writesize,
> d->data = DMACMD_WAIT4END | DMACMD_PIO_WORDS(6);
> d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_READ |
> GPMI_CTRL0_WORD_LENGTH |
> - GPMI_CTRL0_CS(info->cs) |
> + FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
> GPMI_CTRL0_ADDRESS_NAND_DATA |
> (writesize + oobsize);
> d->pio_words[1] = 0;
> @@ -426,7 +394,7 @@ static int mxs_nand_read_page(struct mxs_nand_info *info, int writesize,
> DMACMD_PIO_WORDS(3);
> d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
> GPMI_CTRL0_WORD_LENGTH |
> - GPMI_CTRL0_CS(info->cs) |
> + FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
> GPMI_CTRL0_ADDRESS_NAND_DATA |
> (writesize + oobsize);
> }
> @@ -499,7 +467,7 @@ static int mxs_nand_get_read_status(struct mxs_nand_info *info, void *databuf)
>
> d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE |
> GPMI_CTRL0_WORD_LENGTH |
> - GPMI_CTRL0_CS(info->cs) |
> + FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
> GPMI_CTRL0_ADDRESS_NAND_CLE |
> GPMI_CTRL0_ADDRESS_INCREMENT |
> cmd_queue_len;
> @@ -512,7 +480,7 @@ static int mxs_nand_get_read_status(struct mxs_nand_info *info, void *databuf)
> DMACMD_COMMAND_DMA_WRITE;
> d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_READ |
> GPMI_CTRL0_WORD_LENGTH |
> - GPMI_CTRL0_CS(info->cs) |
> + FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
> GPMI_CTRL0_ADDRESS_NAND_DATA |
> (1);
> d->address = (dma_addr_t)databuf;
> @@ -557,7 +525,7 @@ static int mxs_nand_reset(struct mxs_nand_info *info, void *databuf)
>
> d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE |
> GPMI_CTRL0_WORD_LENGTH |
> - GPMI_CTRL0_CS(info->cs) |
> + FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
> GPMI_CTRL0_ADDRESS_NAND_CLE |
> GPMI_CTRL0_ADDRESS_INCREMENT |
> cmd_queue_len;
> @@ -629,7 +597,7 @@ static int mxs_nand_get_onfi(struct mxs_nand_info *info, void *databuf)
>
> d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE |
> GPMI_CTRL0_WORD_LENGTH |
> - GPMI_CTRL0_CS(info->cs) |
> + FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
> GPMI_CTRL0_ADDRESS_NAND_CLE |
> GPMI_CTRL0_ADDRESS_INCREMENT |
> cmd_queue_len;
> @@ -643,7 +611,7 @@ static int mxs_nand_get_onfi(struct mxs_nand_info *info, void *databuf)
>
> d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
> GPMI_CTRL0_WORD_LENGTH |
> - GPMI_CTRL0_CS(info->cs) |
> + FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
> GPMI_CTRL0_ADDRESS_NAND_DATA;
>
> /* Compile DMA descriptor - read. */
> @@ -654,7 +622,7 @@ static int mxs_nand_get_onfi(struct mxs_nand_info *info, void *databuf)
> DMACMD_COMMAND_DMA_WRITE;
> d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_READ |
> GPMI_CTRL0_WORD_LENGTH |
> - GPMI_CTRL0_CS(info->cs) |
> + FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
> GPMI_CTRL0_ADDRESS_NAND_DATA |
> (sizeof(struct nand_onfi_params));
> d->address = (dma_addr_t)databuf;
> @@ -733,7 +701,7 @@ static int mxs_nand_check_onfi(struct mxs_nand_info *info, void *databuf)
>
> d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE |
> GPMI_CTRL0_WORD_LENGTH |
> - GPMI_CTRL0_CS(info->cs) |
> + FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
> GPMI_CTRL0_ADDRESS_NAND_CLE |
> GPMI_CTRL0_ADDRESS_INCREMENT |
> cmd_queue_len;
> @@ -746,7 +714,7 @@ static int mxs_nand_check_onfi(struct mxs_nand_info *info, void *databuf)
> DMACMD_COMMAND_DMA_WRITE;
> d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_READ |
> GPMI_CTRL0_WORD_LENGTH |
> - GPMI_CTRL0_CS(info->cs) |
> + FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
> GPMI_CTRL0_ADDRESS_NAND_DATA |
> (sizeof(struct onfi_header));
> d->address = (dma_addr_t)databuf;
> @@ -811,7 +779,7 @@ static int mxs_nand_get_readid(struct mxs_nand_info *info, void *databuf)
>
> d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE |
> GPMI_CTRL0_WORD_LENGTH |
> - GPMI_CTRL0_CS(info->cs) |
> + FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
> GPMI_CTRL0_ADDRESS_NAND_CLE |
> GPMI_CTRL0_ADDRESS_INCREMENT |
> cmd_queue_len;
> @@ -824,7 +792,7 @@ static int mxs_nand_get_readid(struct mxs_nand_info *info, void *databuf)
> DMACMD_COMMAND_DMA_WRITE;
> d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_READ |
> GPMI_CTRL0_WORD_LENGTH |
> - GPMI_CTRL0_CS(info->cs) |
> + FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
> GPMI_CTRL0_ADDRESS_NAND_DATA |
> (sizeof(struct readid_data));
> d->address = (dma_addr_t)databuf;
> --
> 2.30.2
>
>
>
