From: Steffen Trumtrar <s.trumtrar@xxxxxxxxxxxxxx>
To optimize the image size, use compressed devicetrees.
Signed-off-by: Steffen Trumtrar <s.trumtrar@xxxxxxxxxxxxxx>
---
arch/arm/boards/reflex-achilles/lowlevel.c | 6 +++---
arch/arm/mach-socfpga/Kconfig | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c
index e213feb9f0..162cd58c58 100644
--- a/arch/arm/boards/reflex-achilles/lowlevel.c
+++ b/arch/arm/boards/reflex-achilles/lowlevel.c
@@ -29,7 +29,7 @@
#define BITSTREAM1_OFFSET 0x0
#define BITSTREAM2_OFFSET BITSTREAM1_OFFSET + SZ_32M
-extern char __dtb_socfpga_arria10_achilles_start[];
+extern char __dtb_z_socfpga_arria10_achilles_start[];
static noinline void achilles_start(void)
{
@@ -86,7 +86,7 @@ ENTRY_FUNCTION(start_socfpga_achilles, r0, r1, r2)
{
void *fdt;
- fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset();
+ fdt = __dtb_z_socfpga_arria10_achilles_start + get_runtime_offset();
barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt);
}
@@ -111,7 +111,7 @@ ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2)
arria10_ddr_calibration_sequence();
- fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset();
+ fdt = __dtb_z_socfpga_arria10_achilles_start + get_runtime_offset();
barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt);
}
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 80344315e3..bdd2a2cfbf 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -23,6 +23,7 @@ config ARCH_SOCFPGA_CYCLONE5
config ARCH_SOCFPGA_ARRIA10
bool
select CPU_V7
+ select ARM_USE_COMPRESSED_DTB
select RESET_CONTROLLER
select HAVE_PBL_MULTI_IMAGES
select OFDEVICE
--
2.30.2
