Older NXP DDR spreadsheets don't initialize ADDRMAP7, leaving it at its POR default of zero. Now that barebox looks at ADDRMAP7 to be able to correctly detect bigger memory sizes, barebox proper on boards with older spreadsheets may read back 4x times as much RAM as actually fitted. MNT Reform LPDDR4 setup already writes 0xf0f (the neutral ignore-me value for the register) into ADDRMAP7. Follow suit for the other i.MX8MQ boards that don't. In-tree Non-i.MX8MQ boards aren't affected. Out of tree boards might and will get a common workaround in a follow-up commit. No workaround for out of tree i.MX8MQ boards. Tested on i.MX8M-EVK (i.MX8MQuad), where now 3G are correctly detected instead of 12G. Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx> --- arch/arm/boards/nxp-imx8mq-evk/ddr_init.c | 3 ++- arch/arm/boards/phytec-som-imx8mq/ddr_init.c | 1 + arch/arm/boards/zii-imx8mq-dev/ddr_init.c | 3 ++- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c index 39addea97320..b1f752c4cb20 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c +++ b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c @@ -81,6 +81,7 @@ void ddr_init(void) reg32_write(0x3d400200,0x15); reg32_write(0x3d40020c,0x0); reg32_write(0x3d400210,0x1f1f); + reg32_write(0x3d40021c,0xf0f); reg32_write(0x3d400204,0x80808); reg32_write(0x3d400214,0x7070707); reg32_write(0x3d400218,0x48080707); @@ -222,4 +223,4 @@ void ddr_init(void) /* enable DDR auto-refresh mode */ tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1; reg32_write(DDRC_RFSHCTL3(0), tmp); -} \ No newline at end of file +} diff --git a/arch/arm/boards/phytec-som-imx8mq/ddr_init.c b/arch/arm/boards/phytec-som-imx8mq/ddr_init.c index aa327d3fb0cb..c6812e3efaec 100644 --- a/arch/arm/boards/phytec-som-imx8mq/ddr_init.c +++ b/arch/arm/boards/phytec-som-imx8mq/ddr_init.c @@ -84,6 +84,7 @@ void ddr_init(void) reg32_write(0x3d400204,0x80808); reg32_write(0x3d400214,0x7070707); reg32_write(0x3d400218,0xf070707); + reg32_write(0x3d40021c,0xf0f); reg32_write(0x3d402020,0x1); reg32_write(0x3d402024,0x518b00); reg32_write(0x3d402050,0x20d040); diff --git a/arch/arm/boards/zii-imx8mq-dev/ddr_init.c b/arch/arm/boards/zii-imx8mq-dev/ddr_init.c index 7a955193fd7c..902d0ee3cd6e 100644 --- a/arch/arm/boards/zii-imx8mq-dev/ddr_init.c +++ b/arch/arm/boards/zii-imx8mq-dev/ddr_init.c @@ -81,6 +81,7 @@ void ddr_init(void) reg32_write(0x3d400200,0x17); reg32_write(0x3d40020c,0x0); reg32_write(0x3d400210,0x1f1f); + reg32_write(0x3d40021c,0xf0f); reg32_write(0x3d400204,0x80808); reg32_write(0x3d400214,0x7070707); reg32_write(0x3d400218,0x7070707); @@ -222,4 +223,4 @@ void ddr_init(void) /* enable DDR auto-refresh mode */ tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1; reg32_write(DDRC_RFSHCTL3(0), tmp); -} \ No newline at end of file +} -- 2.30.2
