Am Freitag, dem 20.05.2022 um 16:33 +0200 schrieb Lucas Stach:
> Hi Teresa,
>
> Am Freitag, dem 20.05.2022 um 14:16 +0000 schrieb Teresa Remmet:
> > Hello Lucas,
> >
> > Am Freitag, dem 13.05.2022 um 16:16 +0200 schrieb Lucas Stach:
> > > The DDRC only uses the DEVICE_CONFIG field for memory types other
> > > than
> > > LPDDR4. While LPDDR4 always has a bus width of x32, the script
> > > aid
> >
> > this is not true for i.MX8M Nano. This SoC has only x16. This is
> > probably why reading the register worked for Joacim on imx8mn.
> > So there is some more checking needed.
> >
> Does the 8MN really use the DEVICE_CONFIG to configure the LPDDR4 bus
> to 16bit width, or does it use the DATA_BUS_WIDTH control to limit
> the
> bus to 16bit?
>
> The register programming aid spreadsheet for the 8MN claims that
> DEVICE_CONFIG has no effect on LPDDR4 memory, same as for all other
> i.M8M* variants. But then the spreadsheet may have copy-and-paste
> issues. So maybe we do in fact need to know that native bus width of
> controller implementation on the specific SoC to get things right for
> LPDDR4?
when looking behind the formulas of the DATA_BUS_WIDTH in the
spreadsheet for i.MX8MN "Full DQ bus width" means always 16bit. For
i.MX8MM + i.MX8MP always 32bit. So yes, I guess we need to check for
the SoC we are running on to get it right.
Regards,
Teresa
>
> Regards,
> Lucas
>
> > Regards,
> > Teresa
> >
> > > generates the value for a x16 bus, as this was apparently used
> > > for
> > > the
> > > controller validation. This resulted in the calculated DRAM size
> > > to
> > > be
> > > halved on boards with LPDDR4 memory.
> > >
> > > Fixes: d8d5778ee8c2 ("ARM: imx: Correct mem size calculation for
> > > 4/8/16/32 bit bus width")
> > > Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> > > ---
> > > arch/arm/mach-imx/esdctl.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-
> > > imx/esdctl.c
> > > index d3dbfff423da..4c8765c193d0 100644
> > > --- a/arch/arm/mach-imx/esdctl.c
> > > +++ b/arch/arm/mach-imx/esdctl.c
> > > @@ -392,7 +392,7 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const
> > > u32
> > > addrmap[],
> > > }
> > >
> > > /* Bus width in bytes, 0 means half byte or 4-bit mode */
> > > - if (is_imx8)
> > > + if (is_imx8 && !(mstr & DDRC_MSTR_LPDDR4))
> > > width = (1 << FIELD_GET(DDRC_MSTR_DEVICE_CONFIG, mstr))
> > > > > 1;
> > > else
> > > width = 4;
> > --
> > PHYTEC Messtechnik GmbH | Robert-Koch-Str. 39 | 55129 Mainz,
> > Germany
> >
> > Geschäftsführer: Dipl.-Ing. Michael Mitezki, Dipl.-Ing. Bodo Huber
> > |
> > Handelsregister Mainz HRB 4656 | Finanzamt Mainz | St.Nr.
> > 266500608, DE
> > 149059855
>
>
--
PHYTEC Messtechnik GmbH | Robert-Koch-Str. 39 | 55129 Mainz, Germany
Geschäftsführer: Dipl.-Ing. Michael Mitezki, Dipl.-Ing. Bodo Huber |
Handelsregister Mainz HRB 4656 | Finanzamt Mainz | St.Nr. 266500608, DE
149059855
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