Hello Sam,
On 15.05.22 21:38, Sam Ravnborg wrote:
> +int at91sam9_sdramc_initialize(const struct at91sam9_sdramc_config *config,
> + unsigned int sdram_address)
> +{
> + unsigned int i;
> +
> + /* Step#1 SDRAM feature must be in the configuration register */
> + sdramc_wr(config, AT91_SDRAMC_CR, config->cr);
> +
> + /* Step#2 For mobile SDRAM, temperature-compensated self refresh(TCSR),... */
> +
> + /* Step#3 The SDRAM memory type must be set in the Memory Device Register */
> + sdramc_wr(config, AT91_SDRAMC_MDR, config->mdr);
> +
> + /* Step#4 The minimum pause of 200 us is provided to precede any single toggle */
> + for (i = 0; i < 1000; i++) ;
This and similar instances below must be replaced by proper delays.
You can use early_udelay for this as you already initialize the PIT.
Did you test SDRAM worked with this setup? I assumed this to be at least
one of the reasons current at91bootstrap fails to work with current compilers
for the 9263. (Newer SoCs use a different DRAM controller and thus a different
driver that doesn't use compile-time removable delay loops).
> +
> + /* Step#5 A NOP command is issued to the SDRAM devices */
> + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NOP);
> + writel(0x00000000, sdram_address);
> +
> + /* Step#6 An All Banks Precharge command is issued to the SDRAM devices */
> + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
> + writel(0x00000000, sdram_address);
> +
> + for (i = 0; i < 10000; i++) ;
> +
> + /* Step#7 Eight auto-refresh cycles are provided */
> + for (i = 0; i < 8; i++) {
> + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);
> + writel(0x00000001 + i, sdram_address + 4 + 4 * i);
> + }
> +
> + /* Pause cycles */
> + for (i = 0; i < 1000; i++) ;
> +
> + /* Step#8 A Mode Register set (MRS) cyscle is issued to program the SDRAM parameters(TCSR, PASR, DS) */
> + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);
> + writel(0xcafedede, sdram_address + 0x24);
> +
> + /* Pause cycles */
> + for (i = 0; i < 1000; i++) ;
> +
> + /* Step#9 For mobile SDRAM initialization, an Extended Mode Register set cycle is issued to ... */
> +
> + /* Step#10 The application must go into Normal Mode, setting Mode to 0 in the Mode Register
> + and perform a write access at any location in the SDRAM. */
> + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL); // Set Normal mode
> + writel(0x00000000, sdram_address); // Perform Normal mode
> +
> + /* Step#11 Write the refresh rate into the count field in the SDRAMC Refresh Timer Rgister. */
> + sdramc_wr(config, AT91_SDRAMC_TR, config->tr);
> +
> + return 0;
> +}
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
> index fe76f60b0..0e05387aa 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
> @@ -181,6 +181,18 @@
> #include <mach/at91sam9261.h>
> #include <mach/at91sam9263.h>
>
> +struct at91sam9_sdramc_config {
> + void __iomem *sdramc;
> + unsigned int mr;
> + unsigned int tr;
> + unsigned int cr;
> + unsigned int lpr;
> + unsigned int mdr;
> +};
> +
> +int at91sam9_sdramc_initialize(const struct at91sam9_sdramc_config *config,
> + unsigned int sdram_address);
> +
> static inline u32 at91_get_sdram_size(void *base)
> {
> u32 val;
--
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