[PATCH v1 2/2] ARM: dts: stm32mp151-prtt1c: add DSA switch and MDIO nodes

[Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx>]

For netboot support we need to configure switch and PHYs. So, provide
needed nodes.

Signed-off-by: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx>
---
 arch/arm/dts/stm32mp151-prtt1c.dts | 124 ++++++++++++++++++++++++++++-
 1 file changed, 120 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/stm32mp151-prtt1c.dts b/arch/arm/dts/stm32mp151-prtt1c.dts
index fc411f9719..4eaf6712a5 100644
--- a/arch/arm/dts/stm32mp151-prtt1c.dts
+++ b/arch/arm/dts/stm32mp151-prtt1c.dts
@@ -22,13 +22,131 @@
 			status = "disabled";
 		};
 	};
+
+	aliases {
+		mdio-gpio0 = &mdio0;
+	};
+
+	clock_ksz9031: clock-ksz9031 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
+
+	mdio0: mdio {
+		compatible = "virtual,mdio-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpios = <&gpioc 1 GPIO_ACTIVE_HIGH
+			 &gpioa 2 GPIO_ACTIVE_HIGH>;
+
+		t1l0_phy: ethernet-phy@6 {
+			compatible = "ethernet-phy-id2000.0181";
+			reg = <6>;
+			interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
+			reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
+		};
+
+		t1l1_phy: ethernet-phy@7 {
+			compatible = "ethernet-phy-id2000.0181";
+			reg = <7>;
+			interrupts-extended = <&gpiog 8 IRQ_TYPE_LEVEL_LOW>;
+			reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>;
+		};
+
+		t1l2_phy: ethernet-phy@10 {
+			compatible = "ethernet-phy-id2000.0181";
+			reg = <10>;
+			interrupts-extended = <&gpiog 10 IRQ_TYPE_LEVEL_LOW>;
+			reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>;
+		};
+
+		rj45_phy: ethernet-phy@2 {
+			reg = <2>;
+			interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>;
+			reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <1000>;
+
+			clocks = <&clock_ksz9031>;
+		};
+	};
+
+	spi-gpio-0 {
+		compatible = "spi-gpio";
+		gpio-sck = <&gpioa 5 GPIO_ACTIVE_HIGH>;
+		gpio-mosi = <&gpiob 5 GPIO_ACTIVE_HIGH>;
+		gpio-miso = <&gpioa 6 GPIO_ACTIVE_HIGH>;
+		cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
+		num-chipselects = <1>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		switch@0 {
+			compatible = "nxp,sja1105q";
+			reg = <0>;
+			spi-max-frequency = <4000000>;
+			spi-rx-delay-us = <1>;
+			spi-tx-delay-us = <1>;
+			spi-cpha;
+
+			reset-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					label = "t1l0";
+					phy-mode = "rmii";
+					phy-handle = <&t1l0_phy>;
+				};
+
+				port@1 {
+					reg = <1>;
+					label = "t1l1";
+					phy-mode = "rmii";
+					phy-handle = <&t1l1_phy>;
+				};
+
+				port@2 {
+					reg = <2>;
+					phy-mode = "rmii";
+					label = "t1l2";
+					phy-handle = <&t1l2_phy>;
+				};
+
+				port@3 {
+					reg = <3>;
+					label = "rj45";
+					phy-handle = <&rj45_phy>;
+					phy-mode = "rgmii-id";
+				};
+
+				port@4 {
+					reg = <4>;
+					label = "cpu";
+					ethernet = <&ethernet0>;
+					phy-mode = "rmii";
+
+					fixed-link {
+						speed = <100>;
+						full-duplex;
+					};
+				};
+			};
+		};
+	};
+
+
 };
 
 &ethernet0 {
 	pinctrl-0 = <&ethernet0_rmii_pins_a>;
 	pinctrl-names = "default";
 	phy-mode = "rmii";
-	phy-reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
 	status = "okay";
 
 	fixed-link {
@@ -57,9 +175,7 @@
 	pins1 {
 		pinmux = <STM32_PINMUX('B', 12, AF11)>, /* ETH1_RMII_TXD0 */
 			 <STM32_PINMUX('B', 13, AF11)>, /* ETH1_RMII_TXD1 */
-			 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
-			 <STM32_PINMUX('A', 2, AF11)>,  /* ETH1_MDIO */
-			 <STM32_PINMUX('C', 1, AF11)>;  /* ETH1_MDC */
+			 <STM32_PINMUX('B', 11, AF11)>; /* ETH1_RMII_TX_EN */
 	};
 	pins2 {
 		pinmux = <STM32_PINMUX('C', 4, AF11)>,  /* ETH1_RMII_RXD0 */
-- 
2.30.2


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