In f04deb4018 was discovered that we used the wrong names for the check
operations. What we named "while_all_bits_clear" really was the
operation "until_all_bits_clear" and likewise for the other operations,
so this patch renamed the operations from "while_*" to "until_*".
Additionally it was assumed that the users have the correct textual
logic, but were compiled to the wrong result. At least for the Karo TX6X
boards it was the other way round though: The texts were wrong, but the
result was correct. This means, although they had the wrong text, the
result was working on the hardware. Now f04deb4018 replaced
"while_all_bits_clear" with "until_all_bits_set" and with this broke
the DCD tables. Fix this by replacing them with the correct commands.
Fixes: f04deb4018 ("i.MX/DCD compiler and interpreter: logic is different")
Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
---
.../boards/karo-tx6x/1600mhz_4x128mx16.imxcfg | 24 +++++++++----------
.../karo-tx6x/flash-header-tx6dl-512m.imxcfg | 11 ++++-----
.../karo-tx6x/flash-header-tx6q-1g.imxcfg | 18 +++++++-------
.../karo-tx6x/flash-header-tx6qp-2g.imxcfg | 18 +++++++-------
4 files changed, 35 insertions(+), 36 deletions(-)
diff --git a/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg
index f11387b023..bd869ec29e 100644
--- a/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg
+++ b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg
@@ -2,13 +2,13 @@
/* MDMISC mirroring interleaved (row/bank/col) */
wm 32 MX6_MMDC_P0_MDMISC 0x00000742
-check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002
+check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002
wm 32 MX6_MMDC_P0_MDSCR 0x00008000
-check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000
wm 32 MX6_MMDC_P0_MDCTL 0x831a0000
-check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000
+check 32 until_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000
wm 32 MX6_MMDC_P0_MDCFG0 0x3f435333
wm 32 MX6_MMDC_P0_MDCFG1 0x926e8a63
@@ -36,7 +36,7 @@ wm 32 MX6_MMDC_P0_MDSCR 0x04008010
wm 32 MX6_MMDC_P0_MDSCR 0x04008040
wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390001
-check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000
+check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000
wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1380000
wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001e001e
@@ -64,11 +64,11 @@ wm 32 MX6_MMDC_P1_MPWRDLCTL 0x40404040
wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
wm 32 MX6_MMDC_P0_MPDGCTRL0 0x80000000
-check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x80000000
+check 32 until_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000
wm 32 MX6_MMDC_P0_MPDGCTRL0 0x80000000
-check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x80000000
+check 32 until_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000
wm 32 MX6_MMDC_P0_MPDGCTRL0 0x50800000
-check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x10001000
+check 32 until_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x10001000
wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
wm 32 MX6_IOM_DRAM_SDQS1 0x00000030
@@ -83,16 +83,16 @@ wm 32 MX6_MMDC_P0_MDSCR 0x04008050
wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030
wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
-check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
wm 32 MX6_MMDC_P0_MDSCR 0x04008050
wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
wm 32 MX6_MMDC_P0_MDSCR 0x04008050
wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
wm 32 MX6_MMDC_P0_MDSCR 0x00008033
wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b
wm 32 MX6_MMDC_P0_MDREF 0x00001800
@@ -100,4 +100,4 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00001006
wm 32 MX6_MMDC_P0_MDPDC 0x0002556d
wm 32 MX6_MMDC_P1_MDPDC 0x0002556d
wm 32 MX6_MMDC_P0_MDSCR 0x00000000
-check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000
diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg
index c327b5f0c1..51f600d490 100644
--- a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg
+++ b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg
@@ -94,11 +94,10 @@ wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333
wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333
wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
wm 32 MX6_MMDC_P0_MDMISC 0x00000742
-check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002
+check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002
wm 32 MX6_MMDC_P0_MDSCR 0x00008000
check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000
wm 32 MX6_MMDC_P0_MDCTL 0x83190000
-check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000
wm 32 MX6_MMDC_P0_MDCFG0 0x3f435333
wm 32 MX6_MMDC_P0_MDCFG1 0xb66e8a63
wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db
@@ -119,7 +118,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001
wm 32 MX6_MMDC_P0_MDSCR 0x04008010
wm 32 MX6_MMDC_P0_MDSCR 0x04008040
wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001
-check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000
+check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000
wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000
wm 32 MX6_MMDC_P0_MDSCR 0x00048033
wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
@@ -128,14 +127,14 @@ wm 32 MX6_IOM_DRAM_SDQS2 0x00000030
wm 32 MX6_IOM_DRAM_SDQS3 0x00000030
wm 32 MX6_MMDC_P0_MDSCR 0x04008050
wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
wm 32 MX6_MMDC_P0_MDSCR 0x04008050
wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
wm 32 MX6_MMDC_P0_MDSCR 0x00008033
wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b
wm 32 MX6_MMDC_P0_MDREF 0x00001800
wm 32 MX6_MMDC_P0_MAPSR 0x00001000
wm 32 MX6_MMDC_P0_MDPDC 0x0002556d
wm 32 MX6_MMDC_P0_MDSCR 0x00000000
-check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000
diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg
index 9c8196d4da..697ce45480 100644
--- a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg
+++ b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg
@@ -121,11 +121,11 @@ wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333
wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
wm 32 MX6_MMDC_P1_MPMUR0 0x00000800
wm 32 MX6_MMDC_P0_MDMISC 0x00000742
-check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002
+check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002
wm 32 MX6_MMDC_P0_MDSCR 0x00008000
-check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000
wm 32 MX6_MMDC_P0_MDCTL 0x831a0000
-check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000
+check 32 until_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000
wm 32 MX6_MMDC_P0_MDCFG0 0x545a79a4
wm 32 MX6_MMDC_P0_MDCFG1 0xff538e64
wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00dd
@@ -147,7 +147,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001
wm 32 MX6_MMDC_P0_MDSCR 0x04008010
wm 32 MX6_MMDC_P0_MDSCR 0x04008040
wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001
-check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000
+check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000
wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000
wm 32 MX6_MMDC_P0_MDSCR 0x00048033
wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
@@ -161,19 +161,19 @@ wm 32 MX6_IOM_DRAM_SDQS7 0x00000030
wm 32 MX6_MMDC_P0_MDSCR 0x04008050
wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030
wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
-check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
wm 32 MX6_MMDC_P0_MDSCR 0x04008050
wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
wm 32 MX6_MMDC_P0_MDSCR 0x04008050
wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
wm 32 MX6_MMDC_P0_MDSCR 0x00008033
wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b
wm 32 MX6_MMDC_P0_MDREF 0x00001800
wm 32 MX6_MMDC_P0_MAPSR 0x00001000
wm 32 MX6_MMDC_P0_MDPDC 0x00025576
wm 32 MX6_MMDC_P0_MDSCR 0x00000000
-check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000
diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg
index c242193a62..8756e8dfb5 100644
--- a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg
+++ b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg
@@ -130,11 +130,11 @@ wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333
wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
wm 32 MX6_MMDC_P1_MPMUR0 0x00000800
wm 32 MX6_MMDC_P0_MDMISC 0x00000742
-check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002
+check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002
wm 32 MX6_MMDC_P0_MDSCR 0x00008000
-check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000
wm 32 MX6_MMDC_P0_MDCTL 0x841a0000
-check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000
+check 32 until_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000
wm 32 MX6_MMDC_P0_MDCFG0 0x898f78f4
wm 32 MX6_MMDC_P0_MDCFG1 0xff328e64
wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db
@@ -157,7 +157,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001
wm 32 MX6_MMDC_P0_MDSCR 0x04008010
wm 32 MX6_MMDC_P0_MDSCR 0x04008040
wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001
-check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000
+check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000
wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000
wm 32 MX6_MMDC_P0_MDSCR 0x00048033
wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
@@ -171,18 +171,18 @@ wm 32 MX6_IOM_DRAM_SDQS7 0x00000030
wm 32 MX6_MMDC_P0_MDSCR 0x04008050
wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030
wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
-check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
wm 32 MX6_MMDC_P0_MDSCR 0x04008050
wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
wm 32 MX6_MMDC_P0_MDSCR 0x04008050
wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
wm 32 MX6_MMDC_P0_MDSCR 0x00008033
wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b
wm 32 MX6_MMDC_P0_MDREF 0x00001800
wm 32 MX6_MMDC_P0_MAPSR 0x00001000
wm 32 MX6_MMDC_P0_MDPDC 0x00025576
wm 32 MX6_MMDC_P0_MDSCR 0x00000000
-check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000
--
2.30.2
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