The i.MX6D and i.MX6Q SoC variants need a workaround for the PFDs which
may not work properly when they are not gated/ungated once during
startup. We currently have this workaround twice, once in the clock
driver and once in imx6_init_lowlevel(). The latter will be removed, but
before doing that the workaround in the clock driver is done
unconditionally and not only when the IPU driver is enabled.
Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
---
drivers/clk/imx/clk-imx6.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index 4f843b8ba7..06cc992b72 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -588,10 +588,6 @@ static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb, struct dev
clks[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", cb + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
clks[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", cb + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
- disable_anatop_clocks(anab);
-
- imx6q_mmdc_ch1_mask_handshake(cb);
-
if (cpu_mx6_has_err009219()) {
/*
* The LDB_DI0/1_SEL muxes should be read-only due to a hardware
@@ -807,6 +803,10 @@ static int imx6_ccm_probe(struct device_d *dev)
clkdev_add_physbase(clks[IMX6QDL_CLK_IPG], MX6_OCOTP_BASE_ADDR, NULL);
+ disable_anatop_clocks(anatop_base);
+
+ imx6q_mmdc_ch1_mask_handshake(ccm_base);
+
if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
imx6_add_video_clks(anatop_base, ccm_base, dev->device_node);
--
2.30.2
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