The imx8 supports a bus width of 4 bits or x4 (device_config b00).
This is a problem for the calculation of the mem size when it only
handle the bus width in bytes. Therefore we must treat the mem size
calculation for the half bus width (width = 0) in a special way.
Do the calculation with one byte width and then divide the mem size
by 2 later on.
Signed-off-by: Joacim Zetterling <joacim.zetterling@xxxxxxxxxxxx>
---
arch/arm/mach-imx/esdctl.c | 30 ++++++++++++++++++++++--------
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index 0e11033b81ae..29333340318b 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -320,6 +320,7 @@ static int vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
#define DDRC_MSTR_LPDDR4 BIT(5)
#define DDRC_MSTR_DATA_BUS_WIDTH GENMASK(13, 12)
#define DDRC_MSTR_ACTIVE_RANKS GENMASK(27, 24)
+#define DDRC_MSTR_DEVICE_CONFIG GENMASK(31, 30)
#define DDRC_ADDRMAP0_CS_BIT1 GENMASK(12, 8)
@@ -364,7 +365,7 @@ static resource_size_t
imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[],
u8 col_max, const u8 col_b[], unsigned int col_b_num,
u8 row_max, const u8 row_b[], unsigned int row_b_num,
- bool reduced_adress_space)
+ bool reduced_adress_space, bool is_imx8)
{
const u32 mstr = readl(ddrc + DDRC_MSTR);
unsigned int banks, ranks, columns, rows, active_ranks, width;
@@ -387,15 +388,20 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[],
BUG();
}
+ /* Bus width in bytes, 0 means half byte or 4-bit mode */
+ if (is_imx8)
+ width = (1 << FIELD_GET(DDRC_MSTR_DEVICE_CONFIG, mstr)) >> 1;
+ else
+ width = 4;
+
switch (FIELD_GET(DDRC_MSTR_DATA_BUS_WIDTH, mstr)) {
case 0b00: /* Full DQ bus */
- width = 4;
break;
- case 0b01: /* Half DQ bus */
- width = 2;
+ case 0b01: /* Half DQ bus */
+ width >>= 1;
break;
case 0b10: /* Quarter DQ bus */
- width = 1;
+ width >>= 2;
break;
default:
BUG();
@@ -422,7 +428,15 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[],
columns = imx_ddrc_count_bits(col_max, col_b, col_b_num);
rows = imx_ddrc_count_bits(row_max, row_b, row_b_num);
- size = memory_sdram_size(columns, rows, 1 << banks, width) << ranks;
+ /*
+ * Special case when bus width is 0 or x4 mode,
+ * calculate the mem size and then divide the size by 2.
+ */
+ if (width)
+ size = memory_sdram_size(columns, rows, 1 << banks, width);
+ else
+ size = memory_sdram_size(columns, rows, 1 << banks, 1) >> 1;
+ size <<= ranks;
return reduced_adress_space ? size * 3 / 4 : size;
}
@@ -470,7 +484,7 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc)
return imx_ddrc_sdram_size(ddrc, addrmap,
12, ARRAY_AND_SIZE(col_b),
16, ARRAY_AND_SIZE(row_b),
- reduced_adress_space);
+ reduced_adress_space, true);
}
static int imx8m_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
@@ -512,7 +526,7 @@ static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc)
return imx_ddrc_sdram_size(ddrc, addrmap,
11, ARRAY_AND_SIZE(col_b),
15, ARRAY_AND_SIZE(row_b),
- reduced_adress_space);
+ reduced_adress_space, false);
}
static int imx7d_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
--
2.25.1
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