The current row calculation in imx_ddrc_sdram_size only handle a
row size up to 16 bit, the row size of the imx8mn DDR4 needs 17 bits.
We need to add DDRC_ADDRMAP7_ROW_B16 and DDRC_ADDRMAP7_ROW_B17 in
the row check table to support a 18 bit row size.
Consulting the reference manual for imx8mm, imx8mn and imx8mq derivates
for 18 bit row size support and it is fin by them.
Signed-off-by: Joacim Zetterling <joacim.zetterling@xxxxxxxxxxxx>
---
arch/arm/mach-imx/esdctl.c | 14 ++++----------
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index e56da3cb76d4..8e2d9e0c115c 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -427,7 +427,8 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc)
readl(ddrc + DDRC_ADDRMAP(4)),
readl(ddrc + DDRC_ADDRMAP(5)),
readl(ddrc + DDRC_ADDRMAP(6)),
- readl(ddrc + DDRC_ADDRMAP(7))
+ readl(ddrc + DDRC_ADDRMAP(7)),
+ readl(ddrc + DDRC_ADDRMAP(8))
};
const u8 col_b[] = {
/*
@@ -445,15 +446,8 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc)
FIELD_GET(DDRC_ADDRMAP2_COL_B4, addrmap[2]),
};
const u8 row_b[] = {
- /*
- * FIXME: RM mentions the following fields as being
- * present, but looking at the code generated by DDR
- * tool it doesn't look like those registers are
- * really implemented/used.
- *
- * FIELD_GET(DDRC_ADDRMAP7_ROW_B17, addrmap[7]),
- * FIELD_GET(DDRC_ADDRMAP7_ROW_B16, addrmap[7]),
- */
+ FIELD_GET(DDRC_ADDRMAP7_ROW_B17, addrmap[7]),
+ FIELD_GET(DDRC_ADDRMAP7_ROW_B16, addrmap[7]),
FIELD_GET(DDRC_ADDRMAP6_ROW_B15, addrmap[6]),
FIELD_GET(DDRC_ADDRMAP6_ROW_B14, addrmap[6]),
FIELD_GET(DDRC_ADDRMAP6_ROW_B13, addrmap[6]),
--
2.25.1
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