On Wed, Feb 23, 2022 at 12:10:36PM +0100, Ahmad Fatoum wrote:
> From: Steffen Trumtrar <s.trumtrar@xxxxxxxxxxxxxx>
>
> Import DT[1] and add the boilerplate to have barebox generate a SSBL
> for the board.
>
> [1]: git://git.phytec.de/tf-a-stm32mp
>
> Signed-off-by: Steffen Trumtrar <s.trumtrar@xxxxxxxxxxxxxx>
> Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
> ---
> arch/arm/boards/Makefile | 1 +
> .../boards/phytec-phycore-stm32mp1/Makefile | 3 +
> .../boards/phytec-phycore-stm32mp1/board.c | 28 ++
> .../boards/phytec-phycore-stm32mp1/lowlevel.c | 19 +
> arch/arm/dts/Makefile | 1 +
> .../dts/stm32mp157c-phycore-stm32mp1-3.dts | 58 +++
> ...stm32mp157c-phycore-stm32mp15-pinctrl.dtsi | 92 +++++
> .../stm32mp157c-phycore-stm32mp15-som.dtsi | 337 ++++++++++++++++++
> arch/arm/mach-stm32mp/Kconfig | 7 +
> images/Makefile.stm32mp | 2 +
> 10 files changed, 548 insertions(+)
> create mode 100644 arch/arm/boards/phytec-phycore-stm32mp1/Makefile
> create mode 100644 arch/arm/boards/phytec-phycore-stm32mp1/board.c
> create mode 100644 arch/arm/boards/phytec-phycore-stm32mp1/lowlevel.c
> create mode 100644 arch/arm/dts/stm32mp157c-phycore-stm32mp1-3.dts
> create mode 100644 arch/arm/dts/stm32mp157c-phycore-stm32mp15-pinctrl.dtsi
> create mode 100644 arch/arm/dts/stm32mp157c-phycore-stm32mp15-som.dtsi
>
> diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
> index 8557e1dca8c6..75e15cbda4df 100644
> --- a/arch/arm/boards/Makefile
> +++ b/arch/arm/boards/Makefile
> @@ -101,6 +101,7 @@ obj-$(CONFIG_MACH_PCM049) += phytec-phycore-omap4460/
> obj-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += phytec-som-am335x/
> obj-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += phytec-som-imx6/
> obj-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += phytec-phycore-imx7/
> +obj-$(CONFIG_MACH_PHYTEC_PHYCORE_STM32MP1) += phytec-phycore-stm32mp1/
> obj-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += phytec-som-imx8mq/
> obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += plathome-openblocks-ax3/
> obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += plathome-openblocks-a6/
> diff --git a/arch/arm/boards/phytec-phycore-stm32mp1/Makefile b/arch/arm/boards/phytec-phycore-stm32mp1/Makefile
> new file mode 100644
> index 000000000000..1d052d28c9fc
> --- /dev/null
> +++ b/arch/arm/boards/phytec-phycore-stm32mp1/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +lwl-y += lowlevel.o
> +obj-y += board.o
> diff --git a/arch/arm/boards/phytec-phycore-stm32mp1/board.c b/arch/arm/boards/phytec-phycore-stm32mp1/board.c
> new file mode 100644
> index 000000000000..eb6147785ff0
> --- /dev/null
> +++ b/arch/arm/boards/phytec-phycore-stm32mp1/board.c
> @@ -0,0 +1,28 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +#include <common.h>
> +#include <driver.h>
> +#include <bootsource.h>
> +
> +static int phycore_stm32mp1_probe(struct device_d *dev)
> +{
> + if (bootsource_get_instance() == 0)
> + of_device_enable_path("/chosen/environment-sd");
> + else
> + of_device_enable_path("/chosen/environment-emmc");
> +
> + barebox_set_hostname("phyCORE-STM32MP1");
> +
> + return 0;
> +}
> +
> +static const struct of_device_id phycore_stm32mp1_of_match[] = {
> + { .compatible = "phytec,phycore-stm32mp1-3" },
> + { /* sentinel */ },
> +};
> +
> +static struct driver_d phycore_stm32mp1_board_driver = {
> + .name = "board-phycore-stm32mp1",
> + .probe = phycore_stm32mp1_probe,
> + .of_compatible = phycore_stm32mp1_of_match,
> +};
> +device_platform_driver(phycore_stm32mp1_board_driver);
> diff --git a/arch/arm/boards/phytec-phycore-stm32mp1/lowlevel.c b/arch/arm/boards/phytec-phycore-stm32mp1/lowlevel.c
> new file mode 100644
> index 000000000000..f76bad86a10a
> --- /dev/null
> +++ b/arch/arm/boards/phytec-phycore-stm32mp1/lowlevel.c
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +#include <common.h>
> +#include <mach/entry.h>
> +#include <debug_ll.h>
> +
> +extern char __dtb_z_stm32mp157c_phycore_stm32mp1_3_start[];
> +
> +ENTRY_FUNCTION(start_phycore_stm32mp1_3, r0, r1, r2)
> +{
> + void *fdt;
> +
> + stm32mp_cpu_lowlevel_init();
> +
> + putc_ll('>');
> +
> + fdt = __dtb_z_stm32mp157c_phycore_stm32mp1_3_start + get_runtime_offset();
> +
> + stm32mp1_barebox_entry(fdt);
> +}
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index e0bb66580f38..925ac12aa52a 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -75,6 +75,7 @@ lwl-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-phycard.dtb.o \
> imx6ull-phytec-phycore-som-nand.dtb.o \
> imx6ull-phytec-phycore-som-emmc.dtb.o
> lwl-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o
> +lwl-$(CONFIG_MACH_PHYTEC_PHYCORE_STM32MP1) += stm32mp157c-phycore-stm32mp1-3.dtb.o
> lwl-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += imx8mq-phytec-phycore-som.dtb.o
> lwl-$(CONFIG_MACH_PINE64_QUARTZ64) += rk3566-quartz64-a.dtb.o
> lwl-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
> diff --git a/arch/arm/dts/stm32mp157c-phycore-stm32mp1-3.dts b/arch/arm/dts/stm32mp157c-phycore-stm32mp1-3.dts
> new file mode 100644
> index 000000000000..351067c9f110
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp157c-phycore-stm32mp1-3.dts
> @@ -0,0 +1,58 @@
> +#include <arm/stm32mp15-pinctrl.dtsi>
> +#include <arm/stm32mp15xxac-pinctrl.dtsi>
> +#include "stm32mp151.dtsi"
> +#include "stm32mp157c-phycore-stm32mp15-som.dtsi"
> +
> +/ {
> + model = "PHYTEC phyCORE-STM32MP1-3 SOM";
> + compatible = "phytec,phycore-stm32mp1-3", "st,stm32mp157";
> +
> + chosen {
> + environment-sd {
> + compatible = "barebox,environment";
> + device-path = &sdmmc1, "partname:barebox-environment";
> + status = "disabled";
> + };
> +
> + environment-emmc {
> + compatible = "barebox,environment";
> + device-path = &sdmmc2, "partname:barebox-environment";
I don't see any partition description for sdmmc1/2. Does the environment
work?
> +&i2c4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c4_pins_a>;
> + i2c-scl-rising-time-ns = <185>;
> + i2c-scl-falling-time-ns = <20>;
> + status = "okay";
> + /delete-property/dmas;
> + /delete-property/dma-names;
> +
> + pmic: stpmic@33 {
> + compatible = "st,stpmic1";
> + reg = <0x33>;
> + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + status = "okay";
Could be dropped.
> +&qspi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
> + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
Why is the reg property overwritten?
> + #address-cells = <1>;
> + #size-cells = <0>;
This is already in the SoC dtsi.
> + status = "disabled";
Is this needed? Isn't the qpsi controller disabled in the SoC dtsi
anyway? There are several more nodes in this files that are explicitly
disabled.
> +
> + flash0: n25q128@0 {
> + compatible = "micron,n25q128a13", "jedec,spi-nor";
> + reg = <0>;
> + spi-rx-bus-width = <4>;
> + spi-max-frequency = <50000000>;
> + m25p,fast-read;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> +};
> +
> +&sdmmc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc1_b4_pins_a>;
> + disable-wp;
> + st,neg-edge;
> + bus-width = <4>;
> + max-frequency = <10000000>;
This is very low. Is this intended?
> + vmmc-supply = <&v3v3>;
> + status = "disabled";
> +};
> +
> +&sdmmc2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
> + non-removable;
> + no-sd;
> + no-sdio;
> + st,neg-edge;
> + bus-width = <8>;
> + vmmc-supply = <&v3v3>;
> + vqmmc-supply = <&v3v3>;
> + mmc-ddr-3_3v;
> + status = "disabled";
> +};
> +
> +&sram {
> + dma_pool: dma_pool@0 {
> + reg = <0x50000 0x10000>;
Should probably be dma_pool@50000
Sascha
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