On 14.01.22 11:12, Oleksij Rempel wrote:
> On Fri, Jan 14, 2022 at 09:30:18AM +0100, Sascha Hauer wrote:
>> On Fri, Jan 14, 2022 at 09:21:41AM +0100, Oleksij Rempel wrote:
>>> At least on RPi2 this clock is 48MHz. This issue was not visible,
>>> becouse amba-pl011 driver was not reseting UART controller after
>>> changing baudrate. So, clk settings was not updated for some time.
>>
>> We have an rpi3 and rpi4 in our lab. Could you give this a test on these
>> boards?
>
> Yes, rpi3 is tested and rpi4 is currently not supported.
Uwe's finger is surely hovering over the send button right now ;)
>
>> Sascha
>>
>>>
>>> Signed-off-by: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx>
>>> ---
>>> arch/arm/boards/raspberry-pi/rpi-common.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c
>>> index 6c5df6fd69..2684bd5ed7 100644
>>> --- a/arch/arm/boards/raspberry-pi/rpi-common.c
>>> +++ b/arch/arm/boards/raspberry-pi/rpi-common.c
>>> @@ -374,7 +374,7 @@ static int rpi_console_clock_init(void)
>>> clk = clk_fixed("apb_pclk", 0);
>>> clk_register_clkdev(clk, "apb_pclk", NULL);
>>>
>>> - clk = clk_fixed("uart0-pl0110", 3 * 1000 * 1000);
>>> + clk = clk_fixed("uart0-pl0110", 48 * 1000 * 1000);
>>> clk_register_clkdev(clk, NULL, "uart0-pl0110");
>>> clkdev_add_physbase(clk, BCM2835_PL011_BASE, NULL);
>>> clkdev_add_physbase(clk, BCM2836_PL011_BASE, NULL);
>>> --
>>> 2.30.2
>>>
>>>
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>>
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>>
>
--
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