On Mon, Nov 15, 2021 at 03:05:39PM +0100, Joacim Zetterling wrote: > On Fri, Nov 05, 2021 at 10:39:27AM +0100, Sascha Hauer wrote: > > Hi Joacim, > > > > On Mon, Nov 01, 2021 at 01:11:09PM +0100, Joacim Zetterling wrote: > > > There was some issues with the imx_ddrc_sdram_size calculation. > > > > > > If we compare the imx8mn DDR4 evk against the LPDDR4 variant in > > > code and in the datasheets, we see the following: > > > > > > DDR4 LPDDR4 > > > ======================== > > > Bus width 16 16 > > > Rank 1 1 > > > Ranks 1 1 > > > Banks 4 8 > > > Banks grps 2 1 > > > Rows 17 15 > > > Col 10 10 > > > > > > This gives us the following problems: > > > > > > 1. Bus width problem. > > > Does not support 16 bit SDRAM bus mode, only 32 bit supported > > > > > > 2. Row size problem. > > > Only up to 16 bit row size support. > > > > > > 3. Bank groups support. > > > Only support of 1 bank group. > > > > > > 4. Bit count problem. > > > The imx_ddrc_count_bits function does not do a correct count. > > > > Could you split this into four patches fixing one problem at a time? > > I am not sure the problems can be separated from each other entirely, > > but splitting this up would make it much easier to understand the > > problems and also their fixes. We'll be glad having smaller patches > > should we ever have to look at this again. > > > > Sascha > I agree with You that the problems can not be separated completely. > But I will try to do my best. Do You prefer a patch set or separately > patches or a combination of them both? A patch set would be fine. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
