On Mon, 23 Aug 2021 14:08:52 +0200 Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx> wrote: Hi Ahmad! > On 17.08.21 12:10, Antony Pavlov wrote: > > barebox timer-riscv driver supports one of user counters: > > > > * 'cycle', counter for RDCYCLE instruction (CSR 0xc00); > > * 'time', timer for RDTIME instruction (CSR 0xc01). > > > > At the moment in M-mode timer-riscv uses the 'cycle' counter, > > and in S-mode timer-riscv uses the 'time' timer. > > > > Alas picorv32 CPU core supports only the 'cycle' counter. > > VexRiscV CPU core in M-mode supports only the 'time' timer. > > > > This patch makes it possible to use the 'time' timer > > for VexRiscV CPU in M-mode. > > > > See also http://lists.infradead.org/pipermail/barebox/2021-May/036067.html > > Comment from earlier series: > > "It also changes the default for M-Mode from cycle to time. > > I can't comment on whether this is ok, I just copied the logic > > from Linux." > > Can you say why this is ok? v4 patch removes riscv_mode() mention from timer-riscv code so timer-riscv uses the 'time' timer by default disregarding M-mode or S-mode is used. I suppose that the 'time' timer is "more popular" than the 'cycle' counter. So IMHO it is ok to use "more popular" feature by default. > > > > > Signed-off-by: Antony Pavlov <antonynpavlov@xxxxxxxxx> > > --- > > arch/riscv/dts/erizo.dtsi | 2 ++ > > drivers/clocksource/timer-riscv.c | 24 ++++++++++++------------ > > 2 files changed, 14 insertions(+), 12 deletions(-) > > > > diff --git a/arch/riscv/dts/erizo.dtsi b/arch/riscv/dts/erizo.dtsi > > index 228711bd69..4eb92ae6f1 100644 > > --- a/arch/riscv/dts/erizo.dtsi > > +++ b/arch/riscv/dts/erizo.dtsi > > @@ -22,6 +22,8 @@ > > > > timebase-frequency = <24000000>; > > > > + barebox,csr-cycle; > > + > > cpu@0 { > > device_type = "cpu"; > > compatible = "cliffordwolf,picorv32", "riscv"; > > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c > > index 5a517fe6b4..96637f988a 100644 > > --- a/drivers/clocksource/timer-riscv.c > > +++ b/drivers/clocksource/timer-riscv.c > > @@ -12,9 +12,8 @@ > > #include <clock.h> > > #include <asm/timer.h> > > #include <asm/csr.h> > > -#include <asm/system.h> > > > > -static u64 notrace riscv_timer_get_count_sbi(void) > > +static u64 notrace riscv_timer_get_count_time(void) > > { > > __maybe_unused u32 hi, lo; > > > > @@ -29,7 +28,7 @@ static u64 notrace riscv_timer_get_count_sbi(void) > > return ((u64)hi << 32) | lo; > > } > > > > -static u64 notrace riscv_timer_get_count_rdcycle(void) > > +static u64 notrace riscv_timer_get_count_cycle(void) > > { > > __maybe_unused u32 hi, lo; > > > > @@ -44,24 +43,25 @@ static u64 notrace riscv_timer_get_count_rdcycle(void) > > return ((u64)hi << 32) | lo; > > } > > > > -static u64 notrace riscv_timer_get_count(void) > > -{ > > - if (riscv_mode() == RISCV_S_MODE) > > - return riscv_timer_get_count_sbi(); > > - else > > - return riscv_timer_get_count_rdcycle(); > > -} > > - > > static struct clocksource riscv_clocksource = { > > - .read = riscv_timer_get_count, > > .mask = CLOCKSOURCE_MASK(64), > > .priority = 100, > > }; > > > > static int riscv_timer_init(struct device_d* dev) > > { > > + struct device_node *cpu; > > + > > dev_dbg(dev, "running at %lu Hz\n", riscv_timebase); > > > > + cpu = of_find_node_by_path("/cpus"); > > + > > + if (of_property_read_bool(cpu, "barebox,csr-cycle")) { > > + riscv_clocksource.read = riscv_timer_get_count_cycle; > > + } else { > > + riscv_clocksource.read = riscv_timer_get_count_time; > > + } > > + > > riscv_clocksource.mult = clocksource_hz2mult(riscv_timebase, riscv_clocksource.shift); > > > > return init_clock(&riscv_clocksource); > > > > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | -- Best regards, Antony Pavlov _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
